Transistor level placement for full custom datapath cell design

Vahia, Durgam; Ciesielski, Maciej

doi:10.1145/299996.300049

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…When electrical connections are made through geometry sharing, area is saved both because of the overlapping geometry and because of the elimination of wiring. In other reported 2D cell synthesis systems • Riepe and Sakallah [Xia et al 1994;Fukui et al 1995;Saika et al 1997;Vahia and Ciesielski 1999;Oskar and Ciesielski 1999;Serdar Sechen 1999] this optimization is performed as a static chaining step before placement. Koan [Cohn et al 1994], which is targeted at analog synthesis, performs no explicit chain formation, but instead allows arbitrary merged structures to form dynamically during placement.…”

Section: Proposed Methodologymentioning

confidence: 99%

Transistor placement for noncomplementary digital VLSI cell synthesis

Riepe

Sakallah²

2003

ACM Trans. Des. Autom. Electron. Syst.

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There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing. Traditional digital cell layout synthesis tools derived from the highly stylized "functional cell" style break down when confronted with such circuit topologies. These cells require a full-custom, two-dimensional layout style which currently requires skilled manual design. In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts. We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains. The primary mechanism for supporting this concurrent optimization is the placement of transistor subchains, diffusion-break-free components of the full transistor chains. When a chain is reordered, transistors may move from one subchain (and therefore one placement component) to another. We will demonstrate how this permits the chain ordering to be optimized for both intra-chain and inter-chain routing. We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool. These experiments make use of a new set of benchmark circuits which provide a rich sample of representative examples in several noncomplementary digital logic families.

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Section: Proposed Methodologymentioning

confidence: 99%

Transistor placement for noncomplementary digital VLSI cell synthesis

Riepe

Sakallah²

2003

ACM Trans. Des. Autom. Electron. Syst.

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“…A non-stochastic approach for digital data path leaf cell design was presented in [20]. This geometry based method only use partial knowledge at any point and hence is greedy in nature.…”

Section: Introductionmentioning

confidence: 99%

AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths

Serdar¹,

Sechen²

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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This paper describes AKORD, a transistor level and mixed transistodgate level placement tool. AKORD has unique layout capabilities that address the digital data path layout problem. In order to improve communication between the placement and routing steps, new post placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. AKORD supports dynamically: 1. Transistor folding without usage of device libraries that contain variants of the same device; 2. Device merging, including information about optimal transistor chain formation; and 3. Well area minimization. Experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest.

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Automatic datapath tile placement and routing

Serdar¹,

Sechen²

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001

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Transistor level placement for full custom datapath cell design

Cited by 6 publications

References 8 publications

Transistor placement for noncomplementary digital VLSI cell synthesis

Transistor placement for noncomplementary digital VLSI cell synthesis

AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths

Automatic datapath tile placement and routing

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