Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM

Bard, K.; Dewey, B.; Hsu, Mei-Ting; Mitchell, Thomas W.; Moody, Karl; Rao, Vasant B.; Rose, R.; Soreff, Jeffrey; Washburn, S. Praveen Samuel

doi:10.1109/jproc.2006.889385

Cited by 6 publications

(2 citation statements)

References 18 publications

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“…The load capacitance and timing analysis for each transistor in the circuit is shown in Table 3, where t d is the delay time of any transistor, t arr is arrival time, and t req is the required time, t s is the slack time. From Table 5, the arrival time equals zero for transistors 1,5,6,8,10,13,16,17,18,19,20 and 26 because these transistors are connected to the circuit's inputs. Also, the required time equals zero for transistors 11, 12, 27 and 28 because these transistors are connected the circuit's outputs as illustrated in Figure 8.…”

Section: Full Adder Circuitmentioning

confidence: 99%

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Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits

Rjoub

Alajlouni

2013

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The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.

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Section: Full Adder Circuitmentioning

confidence: 99%

“…The revolution from the micro-technology to nano-technology and the growing demand on high performance VLSI chips drive industry companies like Intel and IBM to have their own internal tools. These tools are used to estimate CMOS circuit static timing analysis at transistor level in order to design VLSI chips with the best performance [1].…”

Section: Introductionmentioning

confidence: 99%