Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator

Akl, Patrick; Moshovos, Andreas

doi:10.1007/978-3-540-77560-7_18

Cited by 7 publications

(7 citation statements)

References 19 publications

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“…[10] proposes an out-of-order release checkpoint mechanism which reduces the number of RAM checkpoint to about one third. In [11], a ROB-like structure is proposed to accelerate checkpoint recovery. Such structure allows the recovery from selected branches.…”

Section: B Results and Analysismentioning

confidence: 99%

Implementing fast recovery for register alias table in out-of-order processors

Xiao

Lou

et al. 2013

2013 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA)

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Register renaming is an indispensable technique to cope with false data dependencies in out-of-order processors. The critical component for performing register renaming is a register alias table (RAT), which maintains the mappings between architecture and physical registers. Unfortunately, a potential misprediction may seriously slower the processor execution, because new instructions are not allowed to be renamed until the RAT has been restored to the previous correct status. Therefore, a fast RAT recovery is necessary to sustain high performance. As instruction windows size increases, the traditional recovery mechanisms such as using retirement map table and history buffer become too slow. In order to instantly restore RAT from a misprediction, the embedded checkpoint method is introduced but too costly due to creating a large number of checkpoints. In this paper, we propose a selective checkpoint policy which is based on branch confidence and decides when to assign a new checkpoint. Experimental results show that for a 2048-entry large instruction window, our proposal only uses 8 checkpoints to implement fast RAT recovery, reducing the misprediction overhead to just 3% of the ideal model.

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Section: B Results and Analysismentioning

confidence: 99%

Implementing fast recovery for register alias table in out-of-order processors

Xiao

Lou

et al. 2013

2013 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA)

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“…As such, it is potentially synergistic with TurboROB [3], a mechanism that accelerates serial branch recovery. TurboROB also reduces the number of registers that must be held to support minimal recovery.…”

Section: Related Workmentioning

confidence: 97%

CPROB: Checkpoint Processing with Opportunistic Minimal Recovery

Hilton

Eswaran

Roth

2009

2009 18th International Conference on Parallel Architectures and Compilation Techniques

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CPR (Checkpoint Processing and Recovery) is a physical register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style register management. It does so by restricting mis-speculation recovery to checkpoints created at rename, and leveraging this restriction to aggressively reclaim registers that don't appear in checkpoints. The cost of CPR is checkpoint overhead, which is incurred when a mis-speculation occurs on an instruction for which a checkpoint was not created a priori. Here, CPR must recover to the immediately older checkpoint, squashing instructions older than the mis-speculation itself. In contrast, a ROB processor performs minimal recovery and only squashes instructions younger than the mis-speculation.CPROB is a hybrid register management scheme that preserves CPR's aggressive reclamation while opportunistically minimizing checkpoint overhead. CPROB extends CPR to track and hold the registers needed to perform minimal recovery to un-executed branches within each checkpoint. Recovery registers are held on a best-effort basis only. A checkpoint's recovery registers can be freed spontaneously when all branches in the checkpoint execute. They can also be aggressively victimized if dispatch needs registers to proceed. CPROB naturally adapts the register reclamation policy to dynamic branch behavior. When branch mis-predictions are infrequent and registers are needed to support a large window, CPROB victimizes registers and behaves like CPR. When mis-predictions are frequent and the window is small, CPROB holds on to registers and behaves like ROB. As a result, it out-performs both CPR and ROB for a given program. This performance improvement, combined with reduced checkpoint overhead, makes CPROB more energy-efficient than either ROB or CPR.

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“…However, the goal of the work of [15] is not to enhance the performance compared to a traditional ROB design, but instead to maintain a performance level which is close to that of traditional designs, albeit with "simplified" structures. In [3], Akl and Moshovos propose a "Turbo-ROB" mechanism that is used to complement a traditional ROB to support fast state restoration. The Turbo-ROB provides fast recovery for the common case of mispredicted branches, whereas state recoveries in all other instances make use the normal ROB.…”

Section: Related Workmentioning

confidence: 99%

A group-commit mechanism for ROB-based processors implementing the X86 ISA

Afram

Zeng

Ghose

2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

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We introduce an alternative instruction commitment mechanism for a Reorder Buffer (ROB)-based out-of-order processor that commits a group of consecutive instructions atomically to support a larger instruction window. The proposed mechanism makes conservative use of the ROB, by only setting up entries for the instructions that perform the latest update to a register from that group. Further, the destination registers of instructions from a group that do not hold the most recent updates to architectural registers, can be released before the group containing these instructions is committed. The net result is an augmented ROB-based datapath, which increases the effective size of the ROB as well as the effective number of physical registers. The proposed design achieves an average performance gain of about 10% and 16% on the SPEC integer and floating point benchmarks, respectively, when compared to a traditional ROB-based design. The proposed design also achieves a performance gain of slightly over 5% when compared with an aggressive design that uses checkpoints and relatively complex hardware resources.

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Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator

Cited by 7 publications

References 19 publications

Implementing fast recovery for register alias table in out-of-order processors

Implementing fast recovery for register alias table in out-of-order processors

CPROB: Checkpoint Processing with Opportunistic Minimal Recovery

A group-commit mechanism for ROB-based processors implementing the X86 ISA

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