Two channel TI-ADC for communication signals

Harris, Fred; Chen, Xiaofei; Venosa, Elettra; Palmieri, F.

doi:10.1109/spawc.2011.5990478

Cited by 11 publications

(8 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Taking the advantages of CMOS scaling and portability between technology nodes, all-digital calibration techniques eliminate the above analog and mixed-signal issues [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31]. These techniques often focus on one or two types of mismatches among the gain and timing mismatches, without the offset mismatch [13][14][15][16][17][18][19][20][21][22][23][24][25]. The authors in [30] proposed a technique to calibrate all of three above mismatches.…”

Section: U Xmentioning

confidence: 99%

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Hoang

Pham

et al. 2020

Electronics

View full text Add to dashboard Cite

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

show abstract

Section: U Xmentioning

confidence: 99%

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Hoang

Pham

et al. 2020

Electronics

View full text Add to dashboard Cite

show abstract

“…In Paper A of Part II, we propose a two-rate based reconstructor for twochannel TI-ADCs which is a popular TI-ADC configuration [76][77][78][79]. The basic two-rate based approach in Paper A is extended to a general M -channel TI-ADC reconstruction scheme in Paper B.…”

Section: 7(b)mentioning

confidence: 99%

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Pillai¹

2015

View full text Add to dashboard Cite

An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TI-ADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs.iii Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor.Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lowe...

show abstract

“…The reason is the impossibility of FPGAs to reach processing rates beyond the GHz. In fact, although modern Time-Interleaved ADCs [14][15][16] (TI-ADC) are able to provide wide-band signals with sample rates over the GHz, FPGAs are not able to process such signals without decimation and, consequently, without reducing the bandwidth of signals involved in processing [17,18].…”

Section: Introductionmentioning

confidence: 99%

Efﬁcient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

et al. 2019

View full text Add to dashboard Cite

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.

show abstract

Two channel TI-ADC for communication signals

Cited by 11 publications

References 5 publications

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Efﬁcient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

Contact Info

Product

Resources

About