Two-dimensional test data decompressor for multiple scan designs

Zacharia, N.; Rajski, J.; Tyszer, Jerzy; Waicukauski, J.A.

doi:10.1109/test.1996.556961

Cited by 29 publications

(8 citation statements)

References 13 publications

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“…One involves concatenating test cubes [Hellebrand et al 1995a], and the other involves using variable-length seeds [Zacharia 1995;Zacharia et al 1996;Rajski et al 1998a].…”

Section: Previous Workmentioning

confidence: 99%

“…Several techniques for improving the encoding efficiency of the basic LFSR reseeding methodology (originally described in [Könemann 1991]) have been proposed in Hellebrand et al [1992Hellebrand et al [ , 1995aHellebrand et al [ , 1995b, Venkataraman et al [1993], Zacharia [1995], Zacharia et al [1996], and Rajski et al [1998a]. These techniques will be described in detail in Section 2 and compared with the new technique proposed in this article (preliminary results were published in Krishna et al [2001]).…”

Section: Introductionmentioning

confidence: 99%

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Achieving high encoding efficiency with partial dynamic LFSR reseeding

Krishna

Jas

Touba

2004

ACM Trans. Des. Autom. Electron. Syst.

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Previous forms of LFSR reseeding have been static (i.e., test application is stopped while each seed is loaded) and have required full reseeding (i.e., the length of the seed is equal to the length of the LFSR). A new form of LFSR reseeding is described here that is dynamic (i.e., the seed is incrementally modified while test application proceeds) and allows partial reseeding (i.e. length of the seed is less than that of the LFSR). In addition to providing better encoding efficiency, partial dynamic LFSR reseeding has a simpler hardware implementation than previous schemes based on multiple-polynomial LFSRs.

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“…One involves concatenating test cubes [Hellebrand et al 1995a], and the other involves using variable-length seeds [Zacharia 1995;Zacharia et al 1996;Rajski et al 1998a].…”

Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Achieving high encoding efficiency with partial dynamic LFSR reseeding

Krishna

Jas

Touba

2004

ACM Trans. Des. Autom. Electron. Syst.

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“…Variable-length seed approach was proposed in [5] [6]. A larger size of LFSR is used for larger number of specified bits in test cubes, and a smaller size of LFSR is used to encode test cubes with the smaller number of specified bits.…”

Section: Previous Workmentioning

confidence: 99%

Fast seed computation for reseeding shift register in test pattern compression

Kapur

Williams

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to compress test patterns. However, as chip size is growing, solving linear equations requires a large number of computations that is proportional to n 3 . This paper proposes a new scan chain architecture and algorithm so that the order of computation is proportional to the number of scan cells in a chip. The new architecture is a methodology change that does not require complex Design-For-Testability (DFT) as proposed in the previous techniques. Instead of solving linear equations, the proposed new seed computation algorithm topologically determines seeds for test vectors. The compression ratio might be slightly lower than the other approaches, but the proposed approach can handle larger designs in a reasonable amount of time. Computation analysis shows that, for 1 million scan cell design, if we assume it takes 1 msec for the proposed technique to compute seeds, it would take more than 14 minutes for other techniques that solve linear equations.

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“…LFSR reseeding [3,5,8,9,11,12,16,17] is one of the most practical and powerful methods for injecting deterministic patterns in a pseudo-random LFSR sequence. IBM has recently announced test automation tools that support an LFSR reseeding methodology [9].…”

Section: Introductionmentioning

confidence: 99%

A highly regular multi-phase reseeding technique for scan-based BIST

Kalligeros

Kavousianos

Nikolos

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI

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In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. Also, a dynamic reseeding scheme is adopted for further reducing the required hardware overhead. A seed-selection algorithm is moreover presented that, taking advantage of the multi-phase architecture, manages to reduce the number of the required seeds for achieving complete (100 %) fault coverage. Experimental results demonstrate the superiority of the proposed LFSR reseeding approach over the already known reseeding techniques.

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Two-dimensional test data decompressor for multiple scan designs

Cited by 29 publications

References 13 publications

Achieving high encoding efficiency with partial dynamic LFSR reseeding

Achieving high encoding efficiency with partial dynamic LFSR reseeding

Fast seed computation for reseeding shift register in test pattern compression

A highly regular multi-phase reseeding technique for scan-based BIST

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