Two-step annealing effects on ultrathin EOT higher-k (k &amp;#x003D; 40) ALD-HfO&lt;inf&gt;2&lt;/inf&gt; gate stacks

Morita, Yukinori; Migita, Shinji; Mizubayashi, Wataru; Masahara, Meishoku; Ota, Hiroyuki

doi:10.1109/essderc.2012.6343338

Cited by 3 publications

(4 citation statements)

References 14 publications

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“…Therefore, we attribute the decrease in T inv during annealing to an increase in the dielectric constant of the HfO 2 layer. A similar increase in κ has previously been reported during annealing of a Ti-covered HfO 2 layer [16], and has been attributed to oxygen diffusing to the Ti, which facilitates a transition from a readily formed monoclinic phase with κ = 18 to a cubic phase with κ = 40. Similarly, we postulate that oxygen deficient HfO x in our samples facilitates the phase transition to a cubic or tetragonal high-κ phase during annealing [17].…”

Section: Discussionsupporting

confidence: 79%

“…In contrast, T inv decreases by 15% from 11.3 to 9.6 Å, corresponding to an increase of the effective κ from 11.7 to 13.9, determined assuming a constant oxide thickness of 23.8 Å and channel inversion layer thickness of 10.2 Å. These κ values are considerably lower than the reported bulk values of 18 for monoclinic HfO 2 , 40-50 for cubic HfO 2 and 70 for tetragonal HfO 2 [16], [18], [19]. This is expected for the unannealed film, considering the interface layer with a significantly lower κ, but suggests that a relatively small portion of the annealed film is converted to the cubic phase, and that even the annealed film contains residual structural defects, including oxygen vacancies within the HfO 2 layer or at the interfaces, and/or interface roughness reduces the effective κ.…”

Section: Discussionmentioning

confidence: 72%

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SiO2 Free HfO2 Gate Dielectrics by Physical Vapor Deposition

Jamison

Tsunoda

et al. 2015

IEEE Trans. Electron Devices

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HfO 2 layers, 25-Å thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high-κ gate-stack for which the original 8-Å-thick SiO 2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion T inv = 9.7 Å, with a gate leakage J g = 0.8 A/cm 2 . Devices fabricated without in situ annealing of the HfO 2 layer yield a T inv which increases from 10.8 to 11.2 Å as the oxidation time during each HfO 2 growth cycle increases from 10 to 120 s, also causing a decrease in J g from 0.95 to 0.60 A/cm 2 , and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces T inv by 1.5 Å (10%) but also increases the gate leakage by 0.1 A/cm 2 (30%), and causes a 61 mV reduction in V t . These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO 2 , which facilitates both the reduction of an interfacial SiO 2 layer and a partial phase transition to a high-κ cubic or tetragonal HfO 2 phase.Index Terms-HfO 2 , high-k dielectrics, interface scavenging, MOSFET, physical vapor deposition (PVD), SiO 2 interlayer.

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Section: Discussionsupporting

confidence: 79%

Section: Discussionmentioning

confidence: 72%

SiO2 Free HfO2 Gate Dielectrics by Physical Vapor Deposition

Jamison

Tsunoda

et al. 2015

IEEE Trans. Electron Devices

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“…Oxide-silicon and oxide-oxide interfaces strongly affect the equivalent dielectric constant of the gate oxide controlling the electrical performance of an MOS device. Therefore, the equivalent oxide thickness (EOT) is commonly used as an indicator of the electrical performance of an oxide film on silicon, especially the high-k gate oxide of metal-insulator-semiconductor devices [8,9]. Typically, the EOT for an MOS structure is extracted from capacitance-voltage (C-V) measurements obtained at various frequencies, enabling an in-depth understanding of the quality of the oxide-silicon interface [10].…”

Section: Introductionmentioning

confidence: 99%

DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy

Chang,

Wu,

Lin

et al. 2024

Nanomaterials

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This study developed a DC-free technique that used dark-mode scanning capacitance microscopy (DM-SCM) with a small-area contact electrode to evaluate and image equivalent oxide thicknesses (EOTs). In contrast to the conventional capacitance–voltage (C–V) method, which requires a large-area contact electrode and DC voltage sweeping to provide reliable C–V curves from which the EOT can be determined, the proposed method enabled the evaluation of the EOT to a few nanometers for thermal and high-k oxides. The signal intensity equation defining the voltage modulation efficiency in scanning capacitance microscopy (SCM) indicates that thermal oxide films on silicon can serve as calibration references for the establishment of a linear relationship between the SCM signal ratio and the EOT ratio; the EOT is then determined from this relationship. Experimental results for thermal oxide films demonstrated that the EOT obtained using the DM-SCM approach closely matched the value obtained using the typical C–V method for frequencies ranging from 90 kHz to 1 MHz. The percentage differences in EOT values between the C–V and SCM measurements were smaller than 0.5%. For high-k oxide films, DM-SCM with a DC-free operation may mitigate the effect of DC voltages on evaluations of EOTs. In addition, image operations were performed to obtain EOT images showing the EOT variation induced by DC-stress-induced charge trapping. Compared with the typical C–V method, the proposed DM-SCM approach not only provides a DC-free approach for EOT evaluation, but also offers a valuable opportunity to visualize the EOT distribution before and after the application of DC stress.

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“…The physical thickness of the Hf-based dielectric layer is limited to 1.5-2 nm in order to control direct tunneling through the gate stack leading to a total equivalent oxide thickness (EOT) of 0.8 nm for state-of-the-art SiO x /HfO 2 gate stacks. A possible way to further reduce EOT is to employ a higher-k main dielectric layer, either crystallization of HfO 2 into the higher-k tetragonal or cubic phase [3][4][5] or by replacing the HfO 2 layer with another dielectric with a higher-k value e.g. binary or ternary compounds of La [6][7].…”

Section: Introductionmentioning

confidence: 99%

Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs

2014

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Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO 2 /TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ~20% higher electron and hole mobility than literature data on optimized SiO x /HfO 2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.

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Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO<inf>2</inf> gate stacks

Cited by 3 publications

References 14 publications

SiO<sub>2</sub> Free HfO<sub>2</sub> Gate Dielectrics by Physical Vapor Deposition

SiO<sub>2</sub> Free HfO<sub>2</sub> Gate Dielectrics by Physical Vapor Deposition

DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy

Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs

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