Ultra-low on-resistance LDMOS implementation in 0.13&amp;#x00B5;m CD and BiCD process technologies for analog power IC's

Shirai, Kohji; Yonemura, Koji; Watanabe, K.; Kimura, Koji

doi:10.1109/ispsd.2009.5158005

Cited by 18 publications

(3 citation statements)

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“…In the structure of Fig. 7.27a, a common N-well forms the drift region for both transistors, simplifying the process [1,[36][37][38]. Since the N-well is also implanted under the P-body, the substrate and P-body are disconnected from each other.…”

Section: Nldmos Configurationsmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: Nldmos Configurationsmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…Lateral double-diffused MOSFET (LDMOSFET) is widely adopted for medium voltage and smart power applications due to its low onresistance (RON) [1,2] and its compatibility with standard CMOS process [3,4].…”

Section: Introductionmentioning

confidence: 99%

Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation

Tallarico

Reggiani

Depetro

et al. 2018

IEEE Trans. Electron Devices

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In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power LDMOS transistors. When a relatively high drain voltage is applied during the on-state regime, high energetic and/or multiple cold electrons are recognized as the main source of degradation affecting the LDMOS lifetime: the latter is usually extrapolated at typical operating drain voltages. Hence, the extrapolation criterion is particularly critical and different models have been proposed in the past and discussed in this letter. In particular, the dependence of on-resistance degradation (ΔRON) on drain bias is investigated and a simplified extrapolation model, accounting for the saturation effects of the ΔRON at long stress times, is proposed and validated by comparison with experiments and advanced physics-based TCAD simulations, confirming the ability to accurately estimate lifetime on devices featuring short-circuited source-body contacts.

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“…The bipolar-CMOS-DMOS (BCD) process as the process used widely in fabricating the smart power IC is primarily used in the areas of power management IC, motor driver IC and automotive [1,2]. Recently, a number of companies in mobile communication have tried to integrate functions such as power management function, audio/communication function and digital logic function onto one chip.…”

Section: Introductionmentioning

confidence: 99%

Optimization of lateral double-diffused MOS transistors in 0.18 µm bipolar-CMOS-DMOS technology for wide-voltage applications

Choi

Kim

2010

Semicond. Sci. Technol.

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The reduced-surface-field-type lateral double-diffused MOS (LDMOS) structure, which is the key element used in the power device of the bipolar-CMOS-DMOS (BCD) process, was optimized for a wide voltage range of 20-60 V class in the 0.18 μm BCD process. The on-state resistance (R on ) characteristics to the drain-to-source breakdown voltage (BV dss ) have been improved by optimizing the n-drift conditions and related design rules and the reliable safe operating area (SOA) of the device has also been secured for the 20-30 V class LDMOS device. In order to optimize the 40-60 V class LDMOS device, the n-drift drain buffer and low voltage-threshold voltage for the p-channel device implant were introduced and the reliable SOA was obtained while the excellent R on characteristics showed up to the 60 V class. The final trade-off (R on versus BV dss ) characteristics of the LDMOS fabricated under the newly proposed 0.18 μm BCD process have shown competitive characteristics in the wide voltage range for the various applications.

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Ultra-low on-resistance LDMOS implementation in 0.13µm CD and BiCD process technologies for analog power IC's

Cited by 18 publications

References 1 publication

High-Voltage and Power Transistors

High-Voltage and Power Transistors

Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation

Optimization of lateral double-diffused MOS transistors in 0.18 µm bipolar-CMOS-DMOS technology for wide-voltage applications

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