Ultra-Low Power Silicon Neuron Circuit for Extreme-Edge Neuromorphic Intelligence

Rubino, Arianna; Payvand, Melika; Indiveri, Giacomo

doi:10.1109/icecs46596.2019.8964713

Cited by 30 publications

(13 citation statements)

References 31 publications

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“…Our proposed approach has clear advantages for scaling. Table I shows a comparison between our PCM synapse and a CMOS-only implementation in 22 nm FDSOI technology from [28].…”

Section: Discussionmentioning

confidence: 99%

“…On the other hand, mixed-signal analog/digital neuromorphic circuits allow the use of in-memory computing that directly emulates the desired neural and synaptic dynamics using the physics of analog elements [25]- [27]. However, even though progress has been made in extending the duration of synaptic traces using advanced Fully-Depleted Silicon on Insulator (FDSOI) technologies [28], implementing tens-of-secondslong time constants solely based on Complementary Metal-Oxide-Semiconductor (CMOS) is not scalable, as it requires the use of large capacitors. In this paper, we present a novel approach to exploit the drift behavior of Phase Change Memory (PCM) devices to intrinsically perform Eligibility Trace (ET) computation over behavioral timescales.…”

Section: Introductionmentioning

confidence: 99%

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PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

Demirağ

Moro

Dalgaty

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Dedicated hardware implementations of spiking neural networks that combine the advantages of mixed-signal neuromorphic circuits with those of emerging memory technologies have the potential of enabling ultra-low power pervasive sensory processing. To endow these systems with additional flexibility and the ability to learn to solve specific tasks, it is important to develop appropriate on-chip learning mechanisms. Recently, a new class of three-factor spike-based learning rules have been proposed that can solve the temporal credit assignment problem and approximate the error back-propagation algorithm on complex tasks. However, the efficient implementation of these rules on hybrid CMOS/memristive architectures is still an open challenge. Here we present a new neuromorphic building block, called PCM-trace, which exploits the drift behavior of phasechange materials to implement long lasting eligibility traces, a critical ingredient of three-factor learning rules. We demonstrate how the proposed approach improves the area efficiency by > 10× compared to existing solutions and demonstrates a technologically plausible learning algorithm supported by experimental data from device measurements.

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“…Our proposed approach has clear advantages for scaling. Table I shows a comparison between our PCM synapse and a CMOS-only implementation in 22 nm FDSOI technology from [28].…”

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

Demirağ

Moro

Dalgaty

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Fig. 4(d) shows the comparisons between the OCC part and neuron circuits [16], [17], [22]- [24], [28] in terms of the neuron spiking rate and energy consumption per spike. Because only the OCC part performs the synaptic off-current blocking operation via its comparison logic, it can be independently combined with other I & F neuron circuits.…”

Section: Pre-layer Spikementioning

confidence: 99%

“…Thus, without its own learning rule, SNNs exhibit a good performance in inference. Hardware-based neurons have been implemented in the form of electrical circuits emulating the characteristics of the integrate-and-fire (I & F) model [14]- [28]. The I & F neuron circuit accumulates the weighted sum current of the synapses, and creates an action potential instantaneously after the membrane potential (…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, energy-efficient SNNs cannot ignore the idle time of the neuron circuit. Recent studies on silicon neuron circuits [16], [17], [22], [24], [28] and non-silicon materials [18]- [20] exhibit extremely low energy consumption, but their firing rate can still be affected by the synaptic off-current, which is an external off-current component of the neuron circuit.…”

Section: Introductionmentioning

confidence: 99%

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Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

et al. 2021

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In this study, we propose an analog CMOS integrate-and-fire (I & F) neuron circuit with a synaptic off-state current blocking operation. The proposed circuit prevents unintended potential changes in the membrane capacitor owing to the off-state current of synaptic devices, thereby preventing a decrease in the accuracy of the spiking neural network (SNN) inference system. Compared to the conventional I & F neuron circuit, the basic I & F and synaptic off-current blocking operations of the proposed I & F neuron circuit were confirmed in a circuit-level simulation. Furthermore, to verify the effect of the proposed circuit on the neural network, a multi-layer SNN simulation was performed, and the accuracy of the inference system was compared for the conventional and proposed I & F neuron circuits. The simulation and analysis results demonstrate the robustness of the I & F neuron circuit to the drop in accuracy of inference systems due to off-state currents in synaptic devices. INDEX TERMS neuromorphic system, CMOS-based integrate-and-fire (I & F) neuron circuit, spiking neural networks (SNNs), synaptic off-state current blocking operation, TCAD simulation, SPICE simulation, SNN high-level simulation.

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A Reconfigurable Two‐WSe₂‐Transistor Synaptic Cell for Reinforcement Learning

et al. 2022

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learning, reinforcement learning (RL) is one of machine learning paradigms, which allow the machine to interact with the environment and update the policy according to the negative or positive reward signals. [10,11] The algorithms of RL [10] mainly include artificial neural network (ANN)-based deep Q-learning (DQN) and spiking neural network (SNN)based reward-modulated spike-timingdependent plasticity (R-STDP). Compared with ANN-based DQN that adopts error backpropagation and gradient descent to update the weight, R-STDP updates the weight by incorporating the brain-inspired STDP with reward signals being biologically more plausible. [12][13][14][15][16] The hardware implementation of RL paradigm with DQN based on emerging nonvolatile memory technologies (NVMs) has been reported recently. [17][18][19] However, hardware realization of R-STDP based on NVMs is far more less explored. The R-STDP learning rule mainly relies on the modulation of the "standard" STDP by a reward term (positive or negative reward), which is from the external environment, thus realizing SNN-based reinforcement learning. R-STDP stores the traces of synapses that are eligible for STDP (eligibility traces), and applies the modulated weight changes at the time of receiving a positive/negative reward signal. Eligibility traces are a critical ingredient of R-STDP learning rules. [20] There have been some works realizing long-lasting eligibility traces with complementary metal-oxide-semiconductor (CMOS) technology combining large capacitors. [21][22][23][24][25] Recently, Demirağ et al. exploit the drift behavior of phase change memory devices to intrinsically perform eligibility traces with long timescales realizing higher area efficiency than the CMOS ones. [26] In addition to realize eligibility traces constructing STDP, the polarity of STDP will be further changed according to the sign of external reward signal. Thus, it requires emerging nonvolatile devices with reconfigurable characteristics for both STDP and anti-STDP.2D semiconductor field-effect (FE) transistors (FETs) with atomic-level thickness show excellent electrostatic tunability, [27][28][29][30][31][32][33] which provides the possibility of modulating the channel to be reconfigurable p-type or n-type for both STDP and anti-STDP learning rules. On the other hand, to realize nonvolatile memory characteristics, we adopt the ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) as gate dielectric for dynamically tunable memory Reward-modulated spike-timing-dependent plasticity (R-STDP) is a braininspired reinforcement learning (RL) rule, exhibiting potential for decisionmaking tasks and artificial general intelligence. However, the hardware implementation of the reward-modulation process in R-STDP usually requires complicated Si complementary metal-oxide-semiconductor (CMOS) circuit design that causes high power consumption and large footprint. Here, a design with two synaptic transistors (2T) connected in a parallel structure is experimentally demonstrated. The 2T...

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Ultra-Low Power Silicon Neuron Circuit for Extreme-Edge Neuromorphic Intelligence

Cited by 30 publications

References 31 publications

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

A Reconfigurable Two‐WSe₂‐Transistor Synaptic Cell for Reinforcement Learning

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Ultra-Low Power Silicon Neuron Circuit for Extreme-Edge Neuromorphic Intelligence

Cited by 30 publications

References 31 publications

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

A Reconfigurable Two‐WSe2‐Transistor Synaptic Cell for Reinforcement Learning

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A Reconfigurable Two‐WSe₂‐Transistor Synaptic Cell for Reinforcement Learning