Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: smart series switch

Meer, P. R. van der; Staveren, A. van; Roermund, Arthur van

doi:10.1109/iscas.2000.858673

Cited by 18 publications

(8 citation statements)

References 2 publications

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“…However, this technique suffers from two main drawbacks: area overhead and some performance degradation. Another innovative circuit technique to reduce leakage current is the Smart Series Switch (Triple-S) technique which was introduced in [31] by P.R. Meer et al In this technique two parallel switches are connected in series with a leaky device; a low-V th transistor switches as a function of the operation mode (active/standby) and a high-V th transistor switches as a function of the state of the leaky device.…”

Section: B Multi-v Th Techniquesmentioning

confidence: 99%

Leakage sources and possible solutions in nanometer CMOS technologies

Elgharbawy

Bayoumi

2005

IEEE Circuits Syst. Mag.

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Section: B Multi-v Th Techniquesmentioning

confidence: 99%

Leakage sources and possible solutions in nanometer CMOS technologies

Elgharbawy

Bayoumi

2005

IEEE Circuits Syst. Mag.

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“…MTCMOS, leakage feed back, gate-length biasing, and DTCMOS have been applied in flipflops [4][5][6][7][8][9]. MTCMOS technology provides low leakage and high performance operation by utilizing high speed and low V T transistors for logic cells and low leakage and high V T devices as sleep transistors [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A transmission gate flip-flop based on dual-threshold CMOS techniques

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce the leakage power is dual-threshold techniques. Low-threshold transistors are assigned to critical paths of the circuits to enhance the performance, while highthreshold transistors are assigned to non-critical paths to reduce the leakage current. This paper proposes a new transmission gate flip-flop based on dual-threshold CMOS technique to reduce its leakage power. Simulation results show that the proposed transmission gate dual-threshold flip-flop saves 20-30% power and 40-50% leakage power compared with the single-threshold transmission gate one and gate-length biasing one, respectively. The proposed flip-flop is an excellent candidate for low-power VLSI designs in deep sub-micro ICs.

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“…There have been several efforts [Azizi et al 2002;Cao et al 2002;der Meer and Staveren 2000;Hu et al 2002;Kawaguchi et al 2000;Kim et al 2002;Kuroda and Sakurai 1996;Li et al 2002;Mutoh et al 1995;Powell et al 2001;Zhou et al 2001] spanning from the circuit level to the architectural level at reducing the cache leakage energy. Circuit mechanisms include adaptive substrate biasing, dynamic supply scaling, and supply gating.…”

Section: Introductionmentioning

confidence: 99%

Reducing instruction cache energy consumption using a compiler-based strategy

Zhang

Degalahal

et al. 2004

ACM Trans. Archit. Code Optim.

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Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms. We also evaluate the sensitivity of these optimizations to different high-level compiler transformations, energy parameters, and soft errors.

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Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: smart series switch

Cited by 18 publications

References 2 publications

Leakage sources and possible solutions in nanometer CMOS technologies

Leakage sources and possible solutions in nanometer CMOS technologies

A transmission gate flip-flop based on dual-threshold CMOS techniques

Reducing instruction cache energy consumption using a compiler-based strategy

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