Ultrathin Channel Vertical DG MOSFET Fabricated by Using Ion-Bombardment-Retarded Etching

Masahara, Meishoku; Liu, Yongxun; Hosokawa, Shinichi; Matsukawa, Takashi; Ishii, Keisuke; Tanoue, H.; Sakamoto, K.; Sekigawa, Toshihiro; Yamauchi, H.; Kanemaru, S.; Suzuki, Eiichi

doi:10.1109/ted.2004.838335

Cited by 57 publications

(32 citation statements)

References 22 publications

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“…Furthermore, the results clearly demonstrate that the thick FILOX oxide provides excellent protection from the dry etch damage. The values of sub-threshold slope and DIBL approach almost ideal values, which have previously only been reported for thin pillar, fully depleted v-MOSFETs [1][2][3].…”

Section: Discussionsupporting

confidence: 69%

“…Thin pillar, fully-depleted, surround gate v-MOSFETs are being researched as candidates for end-of-roadmap CMOS technology because they have many advantages such as better short channel effects and improved drive current [1][2][3][4][5] per unit area. These devices also offer a steeper sub-threshold slope because the surround gate provides better control of the channel.…”

Section: Introductionmentioning

confidence: 99%

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Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Hakim

Tan

Buiu

et al. 2009

Solid-State Electronics

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a b s t r a c tThis paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of subthreshold slope as the channel length is reduced from 250 to 100 nm, with 100 nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76 mV/dec and a DIBL of 33 mV/V at a channel length of 100 nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81 mV/dec and a DIBL of 25 mV/V at a channel length of 100 nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX process.

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Section: Discussionsupporting

confidence: 69%

Section: Introductionmentioning

confidence: 99%

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Hakim

Tan

Buiu

et al. 2009

Solid-State Electronics

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“…Better SCE immunity also allows the use of low-doped/undoped channels, which improves carrier transport properties (mobility) and reduces dopant fluctuation problems. Scaling the pillar thickness in the fully depleted regime has been shown to deliver excellent subthreshold and drain-induced barrier lowering (DIBL) characteristics, although the expected improvement in drive current has only been demonstrated for pillar diameters of less than 20 nm, where a very strong volume inversion exists in the channel [1], [2]. However, these devices usually require aggressive electron beam lithography and/or complex processing [1]- [4], and so far, no silicidation technology has been reported for these devices.…”

mentioning

confidence: 99%

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Hakim

Tan

Abuelgasim

et al. 2010

IEEE Trans. Electron Devices

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“…One of the solutions is to use a double-gate (DG) field-effect transistor (FET) due mainly to its coupling effects between the top gate and bottom gate. The DG device can not only suppress the SCEs but also improve the transconductance [3], [4]. Although both the processes of the conventional SG and DG devices are compatible to the CMOS technology, the processes of photolithography and the etching for the scaled gate length (L G ) formation are difficult to be realized [4].…”

mentioning

confidence: 99%

A new buried-gate VMOSFET with suppressed overlap capacitance and improved electrical characteristics

Kuo

Lin

Eng

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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This study presents a new buried-gate vertical MOSFET (BGVMOS) with suppressed overlap capacitance and improved electrical characteristics due to its modified gate structure. According to the TCAD simulations, our proposed BGVMOS structure can gain reduced parasitic capacitances (27.11% C gd and 37.53% C gs at V Ds = 1.0 V), improved drain saturation current, and free kink effect, in comparison to a conventional VMOS (CVMOS) structure. Most importantly, the reduced surface scattering in the BGVMOS helps improve the drain current and the transconductance mainly owing to the 1/4 circle gate scheme which is difficult task for a CVMOS transistor. IntroductionIt is more and more difficult to use a planar bulkSi-based single-gate (SG) MOSFET for VLSI applications because of the short-channel effects (SCEs). According to the international technology roadmap for semiconductors (ITRS), the SCEs are difficult to be controlled by using only a SG scheme [1], [2]. One of the solutions is to use a double-gate (DG) field-effect transistor (FET) due mainly to its coupling effects between the top gate and bottom gate. The DG device can not only suppress the SCEs but also improve the transconductance [3], [4]. Although both the processes of the conventional SG and DG devices are compatible to the CMOS technology, the processes of photolithography and the etching for the scaled gate length (L G ) formation are difficult to be realized [4]. Thus, the vertical MOS (VMOS) with DG structure has been considered to be one of the novel device architectures for solving the issues mentioned above. Unfortunately, a large Miller capacitance presented in a conventional VMOS (CVMOS) structure seriously decreases the high 3-dB frequency and affects bandwidth properties. Hence, a large gate-to-source capacitance (C gs ) and a large gate-to-drain capacitance (C gd ) in a CVMOS are shown and compared with a planar bulkSi MOSFET, leading a decrease in the small-signal performance [5], [6].

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Ultrathin Channel Vertical DG MOSFET Fabricated by Using Ion-Bombardment-Retarded Etching

Cited by 57 publications

References 22 publications

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

A new buried-gate VMOSFET with suppressed overlap capacitance and improved electrical characteristics

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