Uniprocessor performance enhancement through adaptive clock frequency control

Uht, Augustus K.

doi:10.1109/tc.2005.34

Cited by 33 publications

(18 citation statements)

References 16 publications

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“…Examples of these devices have been proposed by Dhar [5] and Uht [21]. Periodically, a signal transition is propagated down a delay chain and sampled at the end of the current clock cycle.…”

Section: Previous Workmentioning

confidence: 99%

Razor: a low-power pipeline based on circuit-level timing speculation

Ernst

Kim

Das

et al.

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

912

791

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With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essen- IntroductionA critical concern for embedded systems is the need to deliver high levels of performance given ever-diminishing power budgets. This is evident in the evolution of the mobile phone: in the last 7 years mobile phones have shown a 50X improvement in talk-time per gram of battery 1 , while at the same time taking on new computational tasks that only recently appeared on desktop computers, such as 3D graphics, audio/video, internet access, and gaming. As the breadth of applications for these devices widens, a single operating point is no longer sufficient to efficiently meet their processing and power consumption requirements. For example, MPEG video playback requires an order-of-magnitude higher performance than playing MP3s. However, running at the performance level necessary for video is energy-inefficient for audio. The gap between high performance and low power can be bridged through the use of dynamic voltage scaling (DVS) [16], where periods of low processor utilization are exploited by lowering the clock frequency to the minimum required level, allowing corresponding reduction in the supply voltage. Since dynamic energy scales quadratically with supply voltage, significant reduction in energy use can be obtained [14].Enabling systems to run at multiple frequency and voltage levels is a challenging process and requires characterization of the processor to ensure that its operation remains correct at the required operating points. The minimum possible supply voltage that results in correct operation is referred to as the critical supply voltage. The critical supply voltage must be sufficient to ensure correct operation in the face of a number of environmental and process related variabilities that can impact circuit performance. These include unexpected voltage drops in the power supply network, temperature fluctuations, gate-length and doping concentration variations, cross-coupling noise, etc. These variabilities may be data dependent, meaning that they exhibit their worst-case impact on circuit performance only under certain instruction and data sequences, and are composed of both local and global components. For instance, local process variations will impact specific regions of the die in different and independent ways, while global process variation impacts the circuit performance of the entire die and creates variation from one die to the next. Similarly, temperature and supply drop have local and global components, while cross-coupling noise is a predominantly local effect.To ensure correct operation under all possible variations, a conservative supply voltage is typically selected at designtime using corner analysis. Hence, margins are added ...

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Section: Previous Workmentioning

confidence: 99%

Razor: a low-power pipeline based on circuit-level timing speculation

Ernst

Kim

Das

et al.

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

912

791

View full text Add to dashboard Cite

show abstract

“…Circuit techniques to reduce the effects of voltage noise, such as on-die voltage regulators [28] and voltage-adaptive clocking [29], can reduce voltage and timing margins. We expect some natural reduction in voltage with technology scaling from 0.9V in 28nm down to 0.7V in 7nm, as shown in Table II.…”

Section: Reduced-voltage Operationmentioning

confidence: 99%

Scaling the Power Wall: A Path to Exascale

Villa

Johnson

O'Connor³

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

100

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Abstract-Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.

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“…The first is an infinite impulse response (IIR) filter and, the second, a TEAtime [8], [9] implementation.…”

Section: B Control Block Implementationsmentioning

confidence: 99%

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Pérez-Puigdemont

Calomarde

Moll

2012

2012 IEEE International SOC Conference

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Abstract-In this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the clock period which produces a circuit performance downgrade. We evaluate three self-adaptive clock systems: free running ring oscillator, infinite impulse response filter controlled RO and TEAtime controlled ring oscillator. The safety margin reduction of the three alternatives is investigated under different clock distribution delay conditions, dynamic variation frequencies and the presence of mismatch between the ring oscillator and the critical paths and the delay sensors.

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Uniprocessor performance enhancement through adaptive clock frequency control

Cited by 33 publications

References 16 publications

Razor: a low-power pipeline based on circuit-level timing speculation

Razor: a low-power pipeline based on circuit-level timing speculation

Scaling the Power Wall: A Path to Exascale

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

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