Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits

Abstract

This paper presents an on-chip BiST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the circuit-undertest. The technique is extremely robust and does not require the use of any DSP cores or off-line processing. The resultant architecture has very low overheads (<4% area overhead), ultra fast test times (30µs) and can simply be "plugged" into the RF circuit without the need for any co-design. We present the methodology along with associated circuitry and demonstrate its utility in the self-test of a standard cascode LNA.

Parametrical fault test of CMOS LNA

“…For this reason, we have chosen as test observables the ratios v(f 1 )/v(f 2 ) and v(f 3 )/v(f 2 ). In [5] we have demonstrated that these two observables produce fault coverage similar to the ones suggested in [6], v(f 2 ) and v(f 1 )v(f 3 ), for hard faults like opens or short circuits.…”

“…This constraint greatly simplifies the acquisition of the test observables. For instance, it relaxes the dynamic range requirements of the peak detector K. Suenaga The strategy to test the LNA using the above test circuitry is a structural one based on a three tone test [6]. We measure the response of the LNA to three tones of equal amplitude, one at the central frequency of the RF band (f 2 = 940 MHz) and the two other (f 1 and f 3 ) spaced 100 Mhz above and below roughly at the 3dB corners of the RF band (see Fig.…”

“…Since we do not need any signal amplification at the auxiliary mixer, a passive structure can be used. And finally, the peak detector can be as simple as the circuit proposed in [6].…”

A BIST Technique for RF Voltage-Controlled Oscillators

“…However, the lack of efficient testing techniques, especially for RF parts, has made it difficult to develop the RF SoC products. In order to address such issues, the concept of RF Built-in Self Test (RF BIST) has been proposed in recent years [1]- [3]. With the integration of RF SoC and testing modules in a single chip, the complex RF test is avoided and the throughput can be therefore enhanced.…”