The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-m CMOS RF process.Index Terms-Built-in self-test (BiST) for RF circuits, design for fault tolerance, reliability of RF circuits, RF circuit design.

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This paper presents an on-chip BiST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the circuit-undertest. The technique is extremely robust and does not require the use of any DSP cores or off-line processing. The resultant architecture has very low overheads (<4% area overhead), ultra fast test times (30µs) and can simply be "plugged" into the RF circuit without the need for any co-design. We present the methodology along with associated circuitry and demonstrate its utility in the self-test of a standard cascode LNA.