An ultra-fast, on-chip BiST for RF low noise amplifiers

Gopalan, A.; Das, T.; Washburn, C.; Mukund, P.R.

doi:10.1109/icvd.2005.52

Cited by 20 publications

(13 citation statements)

References 6 publications

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“…This scheme has been applied to LNAs in [26] and [27]. Although the proposed current sensor has very low area overhead (0.1%), it requires far more active and passive elements than the LNA itself.…”

Section: Current Signatures In Testingmentioning

confidence: 99%

Testing RF Components with Supply Current Signatures

Akbay

Sen

Chatterjee

2007

16th Asian Test Symposium (ATS 2007)

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We propose a technique for low-cost testing of radio-frequency components integrating current signatures and alternate test methodology. The technique is suitable for non-invasive built-in test as well as low-cost automated test equipment (ATE) applications. Main features of the technique are (1) minimum loading on signal path by sampling supply current, (2) flexible test stimulus generation based on system constraints, (3) test time reduction by using a single test stimulus and data acquisition, and (4) accurate prediction of all specification values from the single excitation. Two experiments using the proposed implementation demonstrate the accuracy and efficiency of the technique on both single-balanced and double-balanced mixers built with two different technologies.

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Section: Current Signatures In Testingmentioning

confidence: 99%

Testing RF Components with Supply Current Signatures

Akbay

Sen

Chatterjee

2007

16th Asian Test Symposium (ATS 2007)

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“…We then present simulation results to highlight the advantages of the proposed technique over the sense resistor [6] and demonstrate the self-test of a standard cascode LNA.…”

Section: Introductionmentioning

confidence: 99%

“…An on-chip current monitor has been developed to interface with the CUT, and amplify the current information [4]. Ultra-fast test techniques such as the three-tonal approach have also been demonstrated to quantify performance parameters such as Input/Output Match, Gain, and Linearity [6]. In all these instances a resistor has been used as the sensing element, the drop across which is directly proportional to the current in the corresponding circuit branch and serves as the input to the current monitor.…”

Section: Introductionmentioning

confidence: 99%

Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits

Gopalan

Das

Washbum

et al.

2005 IEEE International Symposium on Circuits and Systems

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This paper presents an on-chip BiST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the circuit-undertest. The technique is extremely robust and does not require the use of any DSP cores or off-line processing. The resultant architecture has very low overheads (<4% area overhead), ultra fast test times (30µs) and can simply be "plugged" into the RF circuit without the need for any co-design. We present the methodology along with associated circuitry and demonstrate its utility in the self-test of a standard cascode LNA.

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“…Equation (4) is the core of our previous method, for which the scheme in Fig.2 is valid; based on this, R(t) is expanded in a way that every harmonic component of R(t) is a linear combination of the magnitudes B 1 and B 2 , and hence, the ratio B 2 /B 1 can be ideally derived from the frequency components of a series expansion of R(t). However we have found that R(t) can also be expressed as, (9) where SQ 1 (t) is one of the modulating square-waves previously defined (of period 2T b in this case). That is, the response envelope R(t) can be identified with the square-wave modulation of a low-frequency periodic signal r(t) defined as, (10) whose two harmonic components contain, at much lower frequencies, information about the magnitudes, B 1 and B 2 , of the spectral components of the high-frequency response y(t).…”

Section: Envelope-based Signature Testmentioning

confidence: 99%

Low-cost signature test of RF blocks based on envelope response analysis

Barragán

Fiorelli

Vazquez

et al. 2010

2010 15th IEEE European Test Symposium

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Abstract− This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

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An ultra-fast, on-chip BiST for RF low noise amplifiers

Cited by 20 publications

References 6 publications

Testing RF Components with Supply Current Signatures

Testing RF Components with Supply Current Signatures

Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits

Low-cost signature test of RF blocks based on envelope response analysis

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