Using electrical bitmap results from embedded memory to enhance yield

Segal, J.; Jee, A.; Lepejian, D.; Chu, B.-L.

doi:10.1109/54.922801

Cited by 40 publications

(6 citation statements)

References 9 publications

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“…The failure patterns are some specific shapes formed by the failed cells. Their distributions are used to narrow down the potential defects that cause the failures [2]. Commercial memory testers and their yield analysis tools also support the automatic analysis and location of the failure patterns in the memory bitmap or wafer map [3].…”

Section: Introductionmentioning

confidence: 99%

FAME: a fault-pattern based memory failure analysis framework

Cheng¹,

Wang²,

Lee³

et al. 2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Section: Introductionmentioning

confidence: 99%

FAME: a fault-pattern based memory failure analysis framework

Cheng¹,

Wang²,

Lee³

et al. 2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…By FA and/or process simulation, the possible defects that caused the failures can then be mapped to the failure patterns. In [3,5,6], some of the frequently used failure pattems were discussed. Figure 1 shows four failure pattern examples.…”

Section: Memory Diagnosticsmentioning

confidence: 99%

“…Store the defective-circuit in DC 2) the diameter of the particle defect is D ; 3) the resistance of the particle defect is R; and 4) DC stores the defective circuits (initially, DC = { }) to be simulated.…”

Section: Node-set Up-layer = Truce-allnodefrom -Vvia(lj) Node-setdn-lmentioning

confidence: 99%

“…Based on the analysis results the process can be tuned andlor the design can be modified to enhance the yield. Conventionally, an FA engineer first detects and locates the faulty cell or region, and then performs a series of physical de-processing, e-beam probing, or electron microscope inspection [3,4]. However, without proper methodologies and tools it is more and more difficult to perform the defect-level testing and diagnostics, as we get into the deep-submicron age.…”

Section: Introductionmentioning

confidence: 99%

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Fault pattern oriented defect diagnosis for memories

Wang

Cheng

Lee

et al.

International Test Conference, 2003. Proceedings. ITC 2003.

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Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new developmentjow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.

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“…In a traditional approach, the foundries or Integrated Device Manufacturers use preferentially SRAMs to characterize new process technology [8] due to their specific properties in terms of defect localization. Indeed, SRAM-based test vehicles offer an effective approach to understand marginalities for the process and for the design of SRAM-IP.…”

Section: Introductionmentioning

confidence: 99%

Test chip and infrastructure IP solutions to improve the back-end process during all phases from a new technology development to manufacturing

Forli¹,

Portal²,

Nee³

et al.

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.

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This paper presents a test chip and infrastructure IP (I-IP) solutions to accelerate process development of interconnect on new advanced technology and to improve the back-end-of-line (BEOL) yield on products. The test chip and the I-IP use the same architecture which is described in using a bottom-up approach with emphasis on its scalability. Using this test chip, the specifications of process back-end critical parameters can be quickly and easily analyzed. Using the dedicated infrastructure IP, the defect density tracking as well as the test and diagnosis of process back-end critical parameters can be rapidly and simply performed. To reach this goal, the test flow and its related signature extraction are given. Moreover, each extracted signature is merged in a database which will be used to diagnose defected back-end parameters in the I-IP. Thus, the use of the test chip and the I-IP will allow us to improve the manufacturing process from the beginning of a new technology development and integration to the end of ramp-up production and product manufacturing.

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Using electrical bitmap results from embedded memory to enhance yield

Cited by 40 publications

References 9 publications

FAME: a fault-pattern based memory failure analysis framework

FAME: a fault-pattern based memory failure analysis framework

Fault pattern oriented defect diagnosis for memories

Test chip and infrastructure IP solutions to improve the back-end process during all phases from a new technology development to manufacturing

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