Using the multi-bit feature of memristors for register files in signed-digit arithmetic units

Fey, Dietmar

doi:10.1088/0268-1242/29/10/104008

Cited by 25 publications

(10 citation statements)

References 22 publications

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“…Only a few concepts on multinary memristive logic have been proposed so far. Fey showed a concept for a ternary adder, which uses a fixed number of steps independent of the length of the added words [21,22]. Serb proposed a fuzzy logic concept, which mainly uses advanced peripheral circuitry to implement multinary logic functions [23].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Multinary Łukasiewicz Logic Using Memristive Devices

Bengel

Siemon

Rana

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In the group of emerging non-volatile storage technologies, redox-based memristive devices stand out due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. The opportunity to directly perform Boolean logic operations using memristive devices opens a promising path towards Computation-in-Memory. Recently 7state memristive devices based on TaOx were used to realize a ternary adder circuit as well as a ternary Łukasiewicz logic and fuzzy logic. Logic that uses more than two truth values promises to reduce the number of devices that are needed for a certain operation and thereby further increases the integration density. In this work, we propose a multinary logic for three, five and seven truth values based on the Łukasiewicz logic and show the performance for the implication and negation operation. We, therefore, used the physics-based compact model JART VCM v1b to describe the relation between RESET voltage and high resistive state and then performed the logic operations.

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Section: Introductionmentioning

confidence: 99%

Implementation of Multinary Łukasiewicz Logic Using Memristive Devices

Bengel

Siemon

Rana

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…It has long been known that computing with three states enables 'carry-free addition' in which two operands with wordlength of n can be added in constant time, i.e., independent of n in O(1), whereas binary adders can perform that only in O(log(n)) steps, if reasonable hardware resources are used. In [10], usefulness of multi-level cell memristive devices for ternary computing was shown for the first time.…”

Section: Introductionmentioning

confidence: 99%

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles

Reuben

Fey

2021

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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The movement of data between processing and memory units, often referred to as the 'von Neumann bottleneck' is the main reason for the degraded performance of contemporary computing systems. In an effort to overcome this bottleneck, methods to 'compute' at the location of data are being pursued in many emerging memories, including Resistive RAM (ReRAM). Although many prior works have pursued addition in memory, the latency of n-bit addition has not been judiciously optimized, resulting in O(n) or at best O(log(n)). Computing with three states can enable carry-free addition and result in a latency which is independent of operand width (O(1)). In this work, we propose a method to perform carry-free addition completely in memory (a storage array, a processing array and their peripheral circuitry). The proposed technique incurs a latency of 22 memory cycles, which outperforms other in-memory binary adders for n ≥ 32. This speed is achieved at the cost of increased peripheral hardware.

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“…Over the last few years, this idea has become more popular again motivated by the discovery of the memristor. Architectures exploiting this benefit are published more frequently as, for example, in or. Since Leon Chua proved the theoretical existence of memristors in 1971, many companies tried to find real devices for multilevel nonvolatile memory architectures.…”

Section: Introductionmentioning

confidence: 99%

Case study on memristor‐based multilevel memories

Soell¹,

Reichenbach

Roeber³

et al. 2017

Circuit Theory & Apps

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SUMMARYIn this work, the benefits of memristor-based multilevel memories are described along with their design problems. Starting with measurements of discrete actual devices, a discrete memristor-based multilevel memory is developed. It uses a printed circuit board in order to connect eight packaged memristors from Bio Inspired to test a ternary arithmetic logic unit on a field programmable gate array. These circuits are then integrated in the second proposed memory system based on a 150-nm CMOS process that can be equipped with memristors on top of the metal layers. This integrated solution includes proper read-out, erase, and write circuits to control real memristors and 32×32 memristive memory cells. It is compared with a common static randomaccess memory in terms of area, computation speed, and power consumption showing benefits for memory sizes bigger than 70 words. Because yield and device variations are still a big issue in memristor fabrication, methods to counter these problems are also proposed in the end. An actual implementation should offer several trimming solutions to ensure proper functionality of a prototype memory as well as a power-on calibration, until these problems are solved. The development of the presented memories is not only based on different models but also based on measurements done with real devices.

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Using the multi-bit feature of memristors for register files in signed-digit arithmetic units

Cited by 25 publications

References 22 publications

Implementation of Multinary Łukasiewicz Logic Using Memristive Devices

Implementation of Multinary Łukasiewicz Logic Using Memristive Devices

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles

Case study on memristor‐based multilevel memories

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