Variability impact on on-chip memory data paths

Amat, E.; Calomarde, Antonio; Canal, Ramón; Rubio, Antonio

doi:10.1109/vari.2014.6957086

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…This version focuses on the analysis of sub-V T -level performance; V DD range is set between 0.16 and 0.3 V. When considering the complete system data path (e.g., sense amplifier, multiplexer, and flip-flop), memory cells become the critical component when variability occurs. 19 This is caused by their design with minimum device dimensions, which make them more susceptible to variations. Hence, we concentrate on the cell analysis.…”

Section: Gain-cell Edram Re-designmentioning

confidence: 99%

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

Amat¹,

Calomarde²,

Canal³

et al. 2018

Journal of Low Power Electronics

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Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to achieve the maximum cell performance (i.e., retention time, access time, and energy consumption) suitable for the sub-V T operating level. In this work, we show that asymmetrically resizing the memory cell (i.e., the channel length of the write access transistor and the width of the rest of the devices) results in a 3.5× increase in retention time when compared to the nominal case while reducing area, as well. In terms of reliability (e.g., variability and soft errors), the resizing also improves the cell robustness (50% and 1.9×, respectively) when the cells are operated at sub-V T level.

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Section: Gain-cell Edram Re-designmentioning

confidence: 99%

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

Amat¹,

Calomarde²,

Canal³

et al. 2018

Journal of Low Power Electronics

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“…Since on-chip memories were included in the system, consideration of memory datapath variability against PVT can also be performed. [7].…”

Section: B Razor Characterization Setupmentioning

confidence: 99%

Delay variation compensation through error correction using razor

Chua

Maestro

Alba

et al. 2015

2015 International Workshop on CMOS Variability (VARI)

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The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without Razor, is implemented in 65nm CMOS to accurately characterize the added resiliency introduced by Razor. Functionality testing on the same operating environment allows for a fair characterization by isolating delay dependencies caused by PVT variations.

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Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level

Amat

Calomarde

Canal

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.Peer ReviewedPostprint (author's final draft

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Variability impact on on-chip memory data paths

Cited by 4 publications

References 14 publications

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

Delay variation compensation through error correction using razor

Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level

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Variability impact on on-chip memory data paths

Cited by 4 publications

References 14 publications

Optimization of FinFET-Based Gain Cells for Low Power Sub-VT Embedded DRAMs

Optimization of FinFET-Based Gain Cells for Low Power Sub-VT Embedded DRAMs

Delay variation compensation through error correction using razor

Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level

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Product

Resources

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Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs