Variability Mitigation Mechanisms in Scaled 3T1D-DRAM Memories to 22 nm and Beyond

Abstract

It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how the scaling drawbacks can be compensated through the following: 1) the channel strain of the cell devices and 2) the proposal of new strategies to further enhance the memory cell behavior.

Feasibility of Embedded DRAM Cells on FinFET Technology

“…Additionally, and only for section III, we compare eDRAMs designed with FinFETs and planar devices (22nm HP PTM) [24]. For all the studies, we consider a supply voltage (VDD) of 1V, and to analyze the eDRAM behavior, we measure the following cell parameters: a) Retention Time (RT), time required for the storage node voltage (VS) in the cell to decay to VSmin [25]. This is our reference parameter.…”

Variability impact on on-chip memory data paths

“…larger retention time. This is important as it determines the refresh interval [6]. So then, in this study we compared both implementation types (n/pMOS-based) as a function of supply voltage (0.4-1V); and for different environment temperatures (25º-125ºC).…”

“…Usually, the memory cell is the only focus of circuit analysis, as it is designed by using the minimum feature size for density reasons. At a circuit level, variability translates to performance instabilities, as for instance at memory cell level in the SRAM case SNM instabilities are observed [5]; or reduction of the retention time in the dynamic memories (DRAM) [6]. Nevertheless, a microprocessor is not only implemented by memory cells, and for example a memory access involves also other logics blocks, e.g.…”

New 4T-based DRAM cell designs

“…Different designs of a Dynamic Random-Access Memory (DRAM) cell have been proposed; among them, the 3T1D DRAM cell [1] is a promising scheme due to the small area, the nondestructive read process and the good retention time. However, the operation of this cell is heavily influenced by process fluctuations [3][4][5] and external induced phenomena.…”