Variable domain transformation for linear PAC analysis of mixed-signal systems

Kim, Jaeha; Jones, Kevin D.; Horowitz, Mark

doi:10.1109/iccad.2007.4397376

Cited by 6 publications

(8 citation statements)

References 22 publications

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“…11 plots the jitter transfer functions of the PLL estimated by fitting the measured impulse responses to a second-order linear system model via the LS-CE method [7], along with the simulated results. The PLL jitter transfer was simulated based on the periodic ac analysis described in [11]. The jitter transfer functions exhibit low-pass characteristics with the dc gain of 1 (the PLL multiplication factor was 1), and the estimated damping factors were 0.14, 0.49, and 0.81 for the input frequencies of 128, 256, and 512 MHz, respectively.…”

Section: Measurement Resultsmentioning

confidence: 99%

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

Kim

2009

IEEE Trans. Circuits Syst. II

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This brief describes low-cost on-chip measurement circuits for jitter transfer and supply sensitivity of phase-locked loops (PLLs) and delay-locked loops (DLLs). Unlike previous works that measured the frequency-domain responses, the proposed circuits measure the time-domain responses of the PLL/DLL to the periodic disturbances applied to either its input clock phase or its supply voltage. A synchronous sampling technique accurately measures the PLL/DLL's periodic response while suppressing the unrelated noises and interferences via averaging. The synchronous sampler outputs either dc voltage or digital values, making it suitable for low-cost characterization and production tests. The procedure for estimating the frequency-domain transfer functions from the measured time-domain responses is outlined. The jitter transfer and supply sensitivity measurements were demonstrated with a PLL fabricated in 0.13-µm CMOS. Compared with the PLL that occupied 1.1 × 0.46 mm 2 and dissipated 36 mW from a 1.2-V supply, the on-chip measurement circuits occupied only 0.014 mm 2 and dissipated only 2.6 mW. Index Terms-CMOS, jitter transfer function, on-chip measurement, phase-locked loop (PLL), supply sensitivity.

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Section: Measurement Resultsmentioning

confidence: 99%

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

Kim

2009

IEEE Trans. Circuits Syst. II

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“…We plan to address this, by introducing pragmas that allow for the conversion of a voltage-domain PLL model to the frequency domain. This builds on the domain translation strategy demonstrated by Kim et al [19] and is desirable because typical PLLs have a closed-loop bandwidth of approximately 100-500 KHz in the frequency domain, which allows for a significant reduction in loop sampling frequency.…”

Section: Pll Modeling In the Phase Domainmentioning

confidence: 98%

Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral models

Nothaft

Fernández

Cefali

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Design teams have embraced hardware verification accelerators that enable pre-silicon firmware development. However, emulation is inapplicable for large mixed signal designs. We introduce a methodology that allows for the reuse of analog behavioral models in verification accelerators. We provide a set of pragmas that allow real number models to be converted to fixed point and synthesized and introduce an approach for demonstrating the correctness of these models. We demonstrated this by emulating a large cellular modem within 3,000× the speed of real life, a 3,000,000× speedup over analog simulations, and a 120× speedup over RTL simulations.

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“…In [8], we proposed using variable domain translators to simulate the AC response of a circuit in these non-traditional variables. The variable domain translators are behavioral models written in Verilog-A that translate both large-and small-signal effects in one variable to those in another variable.…”

Section: B Extending Linear Analysismentioning

confidence: 99%

“…Comparison of the phase transfer functions of a 341-transistor PLL simulated by the PAC analysis with variable domain transformation[8] and a transient analysis with sinusoidal input phase modulation.…”

mentioning

confidence: 99%

Leveraging designer's intent: A path toward simpler analog CAD tools

Kim

Jeeradit

Lim

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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Leveraging the Boolean intent of digital circuits has enabled a wide set of CAD tools that helped increase the productivity of digital designers. To increase analog designers' productivity requires a similar encapsulation of designer's intent for analog circuits. We argue that linear system models serve this role for almost all analog circuits, while the variables of these models may be in some transformed domains, rather than being the direct voltage/current waveforms of the circuits. We show how using these models enable new ways to design, optimize, and validate mixed-signal circuits. Even systems that reach steady states only in a stochastic sense can be analyzed as linear systems. Then a remaining issue is to ensure that the non-linear circuit reaches the intended "linear" operating point during start-up, which can be addressed by global convergence analysis.

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Variable domain transformation for linear PAC analysis of mixed-signal systems

Cited by 6 publications

References 22 publications

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral models

Leveraging designer's intent: A path toward simpler analog CAD tools

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