Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node

Leroy, D.; Gaillard, R.; Schaefer, Erwin; Beltrando, C.; Wen, Shi-Jie; Wong, Rick

doi:10.1109/iolts.2008.38

Cited by 8 publications

(2 citation statements)

References 14 publications

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“…1, the alpha cross section increases more than one order of magnitude as the feature size is scaled down from 50 nm to 25 nm. At 25 nm, it is approximately three orders of magnitude lower than that of SRAM cells with a sub-100-nm feature size [3]. Fig.…”

Section: Experimental Set-up and Devices Testedmentioning

confidence: 86%

Alpha-induced soft errors in Floating Gate flash memories

Bagatin

Gerardin

Paccagnella

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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We study the sensitivity to alpha particles of state-of-the-art Multi-Level Cell (MLC) and Single-Level Cell (SLC) NAND Floating Gate (FG) flash memories with NAND architecture. We show that starting from a feature size of 50 nm, MLC flash memories are sensitive to alpha particles, whereas SLC devices do not show any sensitivity down to a feature size of 34 nm. We calculate the alpha-induced soft error rates on the field, discuss technology trends in comparison to heavy-ions

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Section: Experimental Set-up and Devices Testedmentioning

confidence: 86%

Alpha-induced soft errors in Floating Gate flash memories

Bagatin

Gerardin

Paccagnella

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…One of the most researched transient disturbances that can affect the SRAM behavior is Į particle and neutron strike -single event upsets (SEU) causing soft errors [5]. Other transient disturbances like the ones caused by cross talks or inductive couplings should be taken in consideration too.…”

Section: Introductionmentioning

confidence: 99%

Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric

Vatajelu

Gómez-Pau

Renovell

et al. 2011

2011 Asian Test Symposium

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Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin (DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise.

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Reliable Memory Cell Design for Environmental Radiation-Induced Failures in SRAM

Ibe

Osada

2011

Low Power and Reliable SRAM Memory Cell and Array Design

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Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node

Cited by 8 publications

References 14 publications

Alpha-induced soft errors in Floating Gate flash memories

Alpha-induced soft errors in Floating Gate flash memories

Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric

Reliable Memory Cell Design for Environmental Radiation-Induced Failures in SRAM

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