Vector instruction set support for conditional operations

Abstract

Vector instruction sets are receiving renewed interest because of their applicability to multimedia. Current multimedia instruction sets use short vectors with SIMD implementations, but long vector, pipelined implementations have a number of advantages and are a logical next step in multimedia ISA development.Support for conditional operations (as occur in loops containing IF statements) is an important aspect of a vector ISA. Seven ISA alternatives for implementing conditional operations are systematically explored. Performance considerations are discussed through evaluation of a typical IF loop over a range of vector lengths and true conditional values. An approach using masked operations is shown to be one of the better methods, especially if its implementation is able to skip over blocks of false mask bits. Additional analyses of complex IF loops and parallel pipeline implementations support the masked operation approach. The paper concludes with a practical implementation of masked operations that skips over power-of-2-length blocks of false values. This implementation is simpler than skipping arbitrary-length blocks and provides similar performance.

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

“…Support for conditional execution in vector processors is well researched; a good summary is [11]. For short conditionals, implementations that use predicated operations or conditional moves can give good performance.…”

“…Our implementation uses a special mask setup instruction to store the offsets of valid wavefronts in one or more BRAMs within the FPGA. Prior work [11] suggests the idea that each lane can skip forward individually rather than lockstep as entire wavefronts. We take this one step further by allowing the wavefront to be partitioned and separately implement wavefront skipping in each partition.…”

Accelerating divergent applications on SIMD architectures using neural networks

“…SIMD instruction set extensions [1] rely on the core they are tied to for implicit handling of control flow. Similar to the active masks on GPUs, VPU architectures [3] use "vector bit masks" to control the outputs of processing elements; this technique ensures correctness and potentially reduces execution time, but still results in low useful utilization. Some GPUs [2] use "priority scheduling" of warps to hide latency of divergence, but this thread scheduling procedure incurs overhead while only resolving the latency of stalled threads instead of the latency of the divergent threads themselves.…”

“…Single Instruction Multiple Data (SIMD) architectures [1], [2], [3] are well known for their high performance and efficiency in executing data-parallel computation. By definition, SIMD computes multiple data sets in lock-step via wide datapaths under a single control flow.…”

Introducing Control Flow into Vectorized Code

“…A comprehensive survey of vector instructions to support conditional operations is described in [27]. Branchon-superword-condition-codes (BOSCCs) are supported in AltiVec [19], DIVA [7], SSE [12], and other architectures [3,2].…”