Verification of overlap and fringing capacitance models for MOSFETs

Wakita, Naoki; Sato, Naoyuki

doi:10.1016/s0038-1101(99)00331-7

Cited by 10 publications

(2 citation statements)

References 3 publications

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“…Four components can be identified [14]. As was explained previously, those components can be represented by simple capacitive structures, as table 1 shows [15][16][17][18].…”

Section: Gate Capacitance Model and Extraction Proceduresmentioning

confidence: 99%

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Tinoco

Martinez-Lopez

Lezama

et al. 2016

Semicond. Sci. Technol.

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CMOS technology has been guided by the continuous reduction of MOS transistors used to fabricate integrated circuits. Additionally, the use of high-k dielectrics as well as a metal gate electrode have promoted the development of nanometric MOS transistors. Under this scenario, the proper modelling of the gate capacitance, with the aim of adequately evaluating the dielectric film thickness, becomes challenging for nanometric metal-insulator-semiconductor (MIS) structures due to the presence of extrinsic fringing capacitance components which affect the total gate capacitance. In this contribution, a complete intrinsic-extrinsic model for gate capacitance under accumulation of an MIS structure, together with an extraction procedure in order to independently determine the different capacitance components, is presented. ATLAS finite element simulation has been used to validate the proposed methodology.

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“…Four components can be identified [14]. As was explained previously, those components can be represented by simple capacitive structures, as table 1 shows [15][16][17][18].…”

Section: Gate Capacitance Model and Extraction Proceduresmentioning

confidence: 99%

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Tinoco

Martinez-Lopez

Lezama

et al. 2016

Semicond. Sci. Technol.

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“…1(a) has a higher capacitance density than MIM and MOM CAPs, it has a substantial capacitance deviation depending on the bias voltage. [11][12][13][14][15][16][17][18][19][20] There usually are two MOSFET types, which are depletion and enhancement types. Compared with the depletion type, whose threshold voltage is usually negative, the enhancement type (with positive threshold voltage) is more commonly utilized in the integrated circuit design.…”

Section: Introductionmentioning

confidence: 99%

Analysis and simulation of MOSFET-based gate-voltage-independent capacitor

Ojima

et al. 2022

Jpn. J. Appl. Phys.

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In this paper, we analyze the gate capacitance of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and propose a method of realizing the capacitance less dependent on the gate voltage. We analyze the mechanism of capacitance formation in the cases of shorting the source and drain to the ground and floating them. The analysis also reveals the influence of channel length on gate capacitance. By ﬂoating the terminals of source and drain and tuning for an optimum channel length, the voltage dependence of the gate capacitance can be largely reduced. Simulation results verify our analysis, suggesting a possibility of applying a MOSFET capacitor for sample-and-hold circuits which has been applied to the standard-cell-based successive approximation analog-to-digital converter).

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Quasistatic, Non‐Quasistatic, and Noise Models

Bhattacharyya

2009

Compact Mosfet Models for VLSI Design

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Verification of overlap and fringing capacitance models for MOSFETs

Cited by 10 publications

References 3 publications

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Analysis and simulation of MOSFET-based gate-voltage-independent capacitor

Quasistatic, Non‐Quasistatic, and Noise Models

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