Verifying IP-core based system-on-chip designs

Abstract

We describe a methodology for verifying system-on-chip designs. In our methodology, the problem of verifying system-on-chip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, which connects the IP Cores to the buses. Finally, using the verified bus protocols and the IP core designs, the complete system is verified. To illustrate our methodology, we verify the PCI Local Bus, a widely used bus protocol in system-on-chip designs. We demonstrate various modeling and verification techniques for buses by modeling the PCI Local Bus with the symbolic model checker SMV. We have found two potential bugs in the PCI bus protocol specification that await confirmation of the PCI Special Interest Group(PCI-SIG).

Executable Protocol Specification in ESL

“…Therefore, the lack of an exact standard may cause compatibility problems. Even the standard itself has a compatibility problem, as exemplified by the PCI specification Rev 2.2, where the provided state machines conflict with the English specifications [4].…”

A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® Itanium™ Processor Bus Protocol

“…First, formal verification expertise is not required to write the specification. In contrast, many specification frameworks require knowledge of LTL (linear time temporal logic) or CTL (computation tree logic) [CE81] as evidenced by numerous projects such as CMU's PCI specification [CCLW99] and IBM Haifa's FoCs software [ABG + 00]. Because it does not require the complex constructs of these languages, the formal specification can be and has been written in a hardware description language such as Verilog, a language familiar to many engineers.…”

“…In 1999, Chauhan, Clarke, Lu and Wang [CCLW99] specified PCI (Peripheral Component Interconnect) protocol [SIG95] using CTL. Our specification has advantages that a CTL one does not have.…”

Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures

“…There exists an independent body of exercises in formal verification of bus protocols including PCI [7], AMBA [19] and CoreConnect [11]. Such work involved using a model checking tool to verify that a model of the bus system satisfied a set of temporal logic specifications.…”

“…There have been research efforts towards modelling and formal verification of bus architectures [7,11,19], automated synthesis and verification of interfaces between mismatched protocols [6,18]. These efforts have been independently motivated and the semantic disparity of the formalisms used impedes consolidation of solutions from the different areas.…”