2018 76th Device Research Conference (DRC) 2018
DOI: 10.1109/drc.2018.8442215
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Vertical GaN-on-GaN p-n Diodes with 10-A Forward Current and 1.6 kV Breakdown Voltage

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Cited by 5 publications
(4 citation statements)
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“…To avoid the mesa sidewall related leakage currents and associated complications described above, fully vertical p‐n diodes with backside cathode contacts and an ion‐implantation‐based edge termination with sputtered SiNx surface passivation layer have been investigated . To compensate the surface p‐type layer, a nitrogen triple implant was used.…”
Section: Methodsmentioning
confidence: 99%
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“…To avoid the mesa sidewall related leakage currents and associated complications described above, fully vertical p‐n diodes with backside cathode contacts and an ion‐implantation‐based edge termination with sputtered SiNx surface passivation layer have been investigated . To compensate the surface p‐type layer, a nitrogen triple implant was used.…”
Section: Methodsmentioning
confidence: 99%
“…A triple nitrogen implant was used to partially compensate the p‐GaN layer, leaving a thin partially compensated edge termination portion in the regime between the anode and the edge termination etch ring (light blue in Figure b). This optimized thin partially compensated p‐GaN (≈45 nm in this work) was used to manage the lateral electric field distribution near the p + ‐n junction to achieve high breakdown voltage, using a similar working principle to that of reduced surface field (RESURF) diodes . A shallow trench ring was etched using inductively coupled plasma reactive ion etching (ICP‐RIE) to establish the outer boundary of the edge termination structure.…”
Section: Methodsmentioning
confidence: 99%
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“…By lifting off and transferring a high-power vertical pn junction to a copper heat sink (instead of the conventional die attach to the back of the GaN substrate), a 30% reduction in thermal resistance was achieved [7]. In addition, it was found that for a 10 A forward current on a full-thickness GaN substrate, a diode diameter of 1 mm was required [12]; for the same current-carrying capability, a device processed using PEC epitaxial lift-off and transfer was reduced to 550 µm in diameter [13]. This corresponds to a substantial reduction in device area by 70%, and much more efficient use of the GaN substrates.…”
Section: Device Applications and Demonstrationsmentioning
confidence: 99%