Voltage controlled current starved delay cell for Positron Emission Tomography specific DLL based high precision TDC implementation

Mondal, Sabir Ali; Pal, Sourav; Rahaman, Hafizur; Mondal, Pradip Kumar

doi:10.1109/codec.2012.6509270

Cited by 4 publications

(1 citation statement)

References 11 publications

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“…Digital TDCs are mainly based on digital delay lines [6], the most straightforward ones measure time intervals by propagating the START signal in a line of buffers which taps are sampled when the STOP signal arrives, the resultant time resolution is equal to the gate delay in the used technology. To achieve sub-gate delay resolutions many methods have been used such as Vernier Delay Lines [7] DLL TDCs [8] and DLL arrays [9]. In general, TACs offer very good resolutions with low power consumption but they suffer from a limited dynamic range.…”

Section: Introductionmentioning

confidence: 99%

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

Malass

Uhring

Normand

et al. 2017

2017 29th International Conference on Microelectronics (ICM)

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This paper presents the simulations and characterizations results of a hybrid Time to Digital Converter (TDC) fabricated in 180 nm standard CMOS. The design combines the traditional Analog Time to Amplitude Converter (TAC) and Digital TDC techniques to obtain a high adjustable time precision. These approach leads to a 3 bits enhancement of the least significant bit resolution (LSB) for the proposed design. The characterization results showed a time precision of 10 ps with an estimated INL of 5.6 ps rms for a 2.5 ns reference period clock and a 32 cells delay line loop.

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Section: Introductionmentioning

confidence: 99%

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

Malass

Uhring

Normand

et al. 2017

2017 29th International Conference on Microelectronics (ICM)

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A 7.5 ps single-shot precision integrated time counter with segmented delay line

Klepacki

Szplet

Pełka

2014

Review of Scientific Instruments

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This paper describes the design and test results of time interval counter featuring the single-shot precision of 7.5 ps root mean square (rms) and measurement range of 1 ms. These parameters have been achieved by combining direct counting method with a two-stage interpolation within a single clock period. Both stages of interpolation are based on the use of tapped delay lines stabilized by delay locked loop mechanism. In the first stage, a coarse resolution is obtained with the aid of high frequency multiphase clock, while in the second stage a sub-gate delay resolution is achieved with the use of differential delay line. To reduce the nonlinearities of conversion and to improve the precision of measurement, a novel segmented delay line is proposed. An important feature of this segmented delay line is partial overlapping of measurement range and resulting enhancement of both resolution and precision of time interval counter. The maximum integral nonlinearity error of the fine-stage interpolators does not exceed 16 ps and 14 ps in START and STOP interpolators, respectively. These errors have been identified by statistical calibration procedure and corrected to achieve single-shot precision better than 7.5 ps (rms). The time counter is integrated in a single ASIC (Application Specific Integrated Circuit) chip using a standard cost-effective 0.35 μm CMOS (Complementary Metal Oxide Semiconductor) process.

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10-ps Resolution hybrid time to digital converter in a 0.18 μm CMOS technology

Malass

Uhring

Normand

et al. 2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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Voltage controlled current starved delay cell for Positron Emission Tomography specific DLL based high precision TDC implementation

Cited by 4 publications

References 11 publications

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

A 7.5 ps single-shot precision integrated time counter with segmented delay line

10-ps Resolution hybrid time to digital converter in a 0.18 μm CMOS technology

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Voltage controlled current starved delay cell for Positron Emission Tomography specific DLL based high precision TDC implementation

Cited by 4 publications

References 11 publications

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

A 7.5 ps single-shot precision integrated time counter with segmented delay line

10-ps Resolution hybrid time to digital converter in a 0.18 &#x03BC;m CMOS technology

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Product

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10-ps Resolution hybrid time to digital converter in a 0.18 μm CMOS technology