Wafer-Level Heterogeneous Integration for MOEMS, MEMS, and NEMS

Lapisa, Martin; Stemme, G.; Niklaus, Frank

doi:10.1109/jstqe.2010.2093570

Cited by 124 publications

(77 citation statements)

References 98 publications

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“…This can be achieved by using very large-scale heterogeneous integration of the NEM switches on top of high-density metal interconnect layers [22,23]. Figure 3 shows a process for integrating the NEM switches on top of a Si wafer containing planarized metal interconnects.…”

Section: Vlsi Fabricationmentioning

confidence: 99%

“…Finally, the NEM switches are free-etched and the contact materials are deposited onto the switches as shown in Figure 3f, using a similar process as described in Section 2.2. The proposed heterogeneous integration technology is compatible with wafer-level processing and it is capable of implementing NEM switches with nanometer dimensions [22,23].…”

Section: Vlsi Fabricationmentioning

confidence: 99%

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Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Ayala

Grogg

Bazigos

et al. 2015

Solid-State Electronics

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, M. et al. (2015) Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts Abstract Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 µm × 10 µm using 6 NEM switches. Each NEM switch device has a footprint of 5 µm × 3 µm, an air gap of 60 nm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are a key milestone on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

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Section: Vlsi Fabricationmentioning

confidence: 99%

Section: Vlsi Fabricationmentioning

confidence: 99%

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Ayala

Grogg

Bazigos

et al. 2015

Solid-State Electronics

Self Cite

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“…A comprehensive review of heterogeneous integration technologies is provided in [18]. Complex multi-layer bolometer structures with a pixel pitch of down to 17 um have already been demonstrated [7].…”

Section: Heterogeneous Integration Of Mems Bolometers On Ic Wafersmentioning

confidence: 99%

“…Emerging very large scale heterogeneous 3D integration technologies for combining high-performance MEMS (Microelectromechanical System) on top of CMOS-based integrated circuit (IC) wafers provide opportunities to decouple the fabrication of the CMOS circuits and the manufacturing of the MEMS [18][19][20][21][22][23]. Thus, for IR bolometer applications the thermistor material can be manufactured and optimized using high-quality epitaxial deposition processes at elevated temperatures.…”

Section: Introductionmentioning

confidence: 99%

Micromechanical Process Integration and Material Optimization for High Performance Silicon-Germanium Bolometers

Malm¹,

Kolahdouz²,

Forsberg

et al. 2012

MRS Proc.

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Semiconductor-based thermistors are very attractive sensor materials for uncooled thermal infrared (IR) bolometers. Very large scale heterogeneous integration of MEMS is an emerging technology that allows the integration of epitaxially grown, high-performance IR bolometer thermistor materials with pre-processed CMOS-based integrated circuits for the sensor read-out. Thermistor materials based on alternating silicon (Si) and silicon-germanium (SiGe) epitaxial layers have been demonstrated and their performance is continuously increasing. Compared to a single layer of silicon or SiGe, the temperature coefficient of resistance (TCR) can be strongly enhanced to about 3 %/K, by using thin alternating layers. In this paper we report on the optimization of alternating Si/SiGe layers by advanced physically based simulations, including quantum mechanical corrections. Our simulation framework provides reliable predictions for a wide range of SiGe layer compositions, including concentration gradients. Finally, our SiGe thermistor layers have been evaluated in terms of low-frequency noise performance, in order to optimize the bolometer detectivity.

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“…3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6]. …”

mentioning

confidence: 99%

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Fischer

Bleiker

Somjit

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications. IntroductionDuring the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6].

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Wafer-Level Heterogeneous Integration for MOEMS, MEMS, and NEMS

Cited by 124 publications

References 98 publications

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Micromechanical Process Integration and Material Optimization for High Performance Silicon-Germanium Bolometers

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

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