Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit

Licciardo, Gian Domenico; Cappetta, Carmine; Benedetto, Luigi Di; Vigliar, Mario

doi:10.1109/tcsii.2016.2546899

Cited by 27 publications

(5 citation statements)

References 18 publications

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“…Indeed, the FCN achieves state-of-the-art recognition accuracy both for laying and sitting postures, by exploiting only pressure sensors grouped in a small area close to the FCN, according to the edge-computing paradigm [28,29], without any particular distribution strategy. The FCN implements an end-to-end classification by exploiting a base-2 quantization scheme for weights and binarized activations [30,31] to meet the optimal trade-off between high recognition accuracy, the number of mapped physical resources and low power consumption [32,33]. The FCN achieves an average accuracy of 96.77% and 98.88% to classify laying and sitting postures, respectively.…”

Section: Introductionmentioning

confidence: 99%

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

et al. 2021

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A custom HW design of a Fully Convolutional Neural Network (FCN) is presented in this paper to implement an embeddable Human Posture Recognition (HPR) system capable of very high accuracy both for laying and sitting posture recognition. The FCN exploits a new base-2 quantization scheme for weight and binarized activations to meet the optimal trade-off between low power dissipation, a very reduced set of instantiated physical resources and state-of-the-art accuracy to classify human postures. By using a limited number of pressure sensors only, the optimized HW implementation allows keeping the computation close to the data sources according to the edge computing paradigm and enables the design of embedded HP systems. The FCN can be simply reconfigured to be used for laying and sitting posture recognition. Tested on a public dataset for in-bed posture classification, the proposed FCN obtains a mean accuracy value of 96.77% to recognize 17 different postures, while a small custom dataset has been used for training and testing for sitting posture recognition, where the FCN achieves 98.88% accuracy to recognize eight positions. The FCN has been prototyped on a Xilinx Artix 7 FPGA where it exhibits a dynamic power dissipation lower than 11 mW and 7 mW for laying and sitting posture recognition, respectively, and a maximum operation frequency of 47.64 MHz and 26.6 MHz, corresponding to an Output Data Rate (ODR) of the sensors of 16.50 kHz and 9.13 kHz, respectively. Furthermore, synthesis results with a CMOS 130 nm technology have been reported, to give an estimation about the possibility of an in-sensor circuital implementation.

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Section: Introductionmentioning

confidence: 99%

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

et al. 2021

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“…In future, they intended to apply it for larger designs. Licciardo et al [14] used a novel radix-3 partitioning method for better floating point operations. Wirthlin, M. [15] explored high-reliability systems made up of FPGA designs that exploit programmability.…”

Section: Related Workmentioning

confidence: 99%

Approximate Computing Based Low-Power FPGA Design for Big Data Analytics in Cloud Environments

Dova,

M Sandi

2024

SCPE

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As cloud computing continues to evolve, the demand for scalable and energy-efficient infrastructure to handle extensive applications becomes paramount. Traditional transistor scaling and microprocessor design methods no longer suffice to meet the growing scale of cloud usage. This research explores the potential of approximate computing (AC) as an innovative solution to these challenges, particularly in high-demand computational settings. AC, known for its ability to make controlled accuracy trade-offs, is identified as a key strategy for improving both the performance and energy efficiency of cloud infrastructure, with a focus on low-power Field-Programmable Gate Array (FPGA) designs. This paper introduces novel methodologies that harness the strengths of AC, emphasizing its application in neural-based and machine-learning techniques for energy-efficient solutions. By targeting the performance of AC, especially in varied application domains and complex data mining scenarios, we propose two groundbreaking approaches that significantly enhance computational speed and reduce energy consumption. Our empirical analysis demonstrates notable improvements over existing techniques, highlighting the effectiveness of AC in optimizing cloud infrastructure. The proposed model on FPGA through cloud computing attains substantial elevation rates by 89 % and energy reduction by 122%, which had been good outcomes. This study not only confirms the benefits of integrating AC with low-power FPGA designs for cloud environments but also sets a new benchmark for future research in achieving more sustainable and efficient cloud computing via VLSI FGPA design analysis solutions.

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“… A new custom partial-binarization schema has been used for both the encoder and the decoder, to feature binarized weights and non-binarized activations for some selected layers.  The number of physical resources needed by the AE implementation has been limited thanks to a careful custom HW design rather than by reducing the number of layers [10]- [14].  This choice takes advantage of the low number of activations of the classifier and enables the possibility of sharing it with multiple AEs integrated into several sensors distributed on the apparatus under monitoring.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Detection and Classification for In-Sensor Predictive Maintenance Based on Vibration Monitoring

et al. 2022

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In this work, a new custom design of an anomaly detection and classification system is proposed. It is composed of a convolutional Auto-Encoder (AE) hardware design to perform anomaly detection which cooperates with a mixed HW/SW Convolutional Neural Network (CNN) to perform the classification of detected anomalies. The AE features a partial binarization, so that the weights are binarized while the activations, associated to some selected layers, are non-binarized. This has been necessary to meet the severe area and energy constraints that allow it to be integrated on the same die as the MEMS sensors for which it serves as a neural accelerator. The CNN shares the feature extraction module with the AE, whereas a SW classifier is triggered by the AE when a fault is detected, working asynchronously to it. The AE has been mapped on a Xilinx Artix-7 FPGA, featuring an Output Data Rate (ODR) of 365 kHz and achieving a power dissipation of 333 W/MHz. Logic synthesis has targeted TSMC CMOS 65 nm, 90 nm, and 130 nm standard cells. Best results achieved highlight a power consumption of 138 μW/MHz with an area occupation of 0.49 mm 2 when real-time operations are set. These results enable the integration of the complete neural accelerator in the CMOS circuitry that typically sits with the inertial MEMS on the same silicon die. Comparisons with the related works suggest that the proposed system is capable of state-of-the-art performances and accuracy.

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Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit

Cited by 27 publications

References 18 publications

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

Approximate Computing Based Low-Power FPGA Design for Big Data Analytics in Cloud Environments

Low-Power Detection and Classification for In-Sensor Predictive Maintenance Based on Vibration Monitoring

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