Working with Process Variation Aware Caches

Mutyam, Madhu; Narayanan,

doi:10.1109/date.2007.364450

Cited by 19 publications

(14 citation statements)

References 15 publications

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“…To minimize the number of imperfect cache sets, we introduce a technique called line reshuffling, which is similar to block rearrangement techniques proposed by Mutyam and Narayanan [2007]. They considered block rearrangement either between a pair of two adjacent cache sets or among all cache sets.…”

Section: Minimizing the Number Of Imperfect Cache Sets And Encoding Cmentioning

confidence: 99%

“…The results are given for a cache where 25% of the lines are imperfect. Our performance results are based on the assumption that a specific percentage of cache lines are affected by process variation and such lines are randomly distributed over the cache as in Mutyam and Narayanan [2007]. The second bar plots the performance value of the access mechanism based on the worst-case access latency paradigm (Delayed); where each cache access takes two cycles.…”

Section: Egalitarian Cache Management Under Process Variationmentioning

confidence: 99%

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Hardware/software approaches for reducing the process variation impact on instruction fetches

Kadayif

Turkcan

Kiziltepe

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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As technology moves towards finer process geometries, it is becoming extremely difficult to control critical physical parameters such as channel length, gate oxide thickness, and dopant ion concentration. Variations in these parameters lead to dramatic variations in access latencies in Static Random Access Memory (SRAM) devices. This means that different lines of the same cache may have different access latencies. A simple solution to this problem is to adopt the worst-case latency paradigm. While this egalitarian cache management is simple, it may introduce significant performance overhead during instruction fetches when both address translation (instruction Translation Lookaside Buffer (TLB) access) and instruction cache access take place, making this solution infeasible for future high-performance processors. In this study, we first propose some hardware and software enhancements and then, based on those, investigate several techniques to mitigate the effect of process variation on the instruction fetch pipeline stage in modern processors. For address translation, we study an approach that performs the virtual-to-physical page translation once, then stores it in a special register, reusing it as long as the execution remains on the same instruction page. To handle varying access latencies across different instruction cache lines, we annotate the cache access latency of instructions within themselves to give the circuitry a hint about how long to wait for the next instruction to become available. © 2013 ACM

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Section: Minimizing the Number Of Imperfect Cache Sets And Encoding Cmentioning

confidence: 99%

Section: Egalitarian Cache Management Under Process Variationmentioning

confidence: 99%

Hardware/software approaches for reducing the process variation impact on instruction fetches

Kadayif

Turkcan

Kiziltepe

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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show abstract

“…In traditional caches, a memory block mapped to a faulty line/set is statically remapped to another good line/set [12][13][14]. Such schemes increase the number of conflict misses since the remapped cache line/set is now shared by more memory addresses.…”

Section: Additional Benefitsmentioning

confidence: 99%

A novel cache architecture with enhanced performance and security

Wang

Lee

2008

2008 41st IEEE/ACM International Symposium on Microarchitecture

113

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Abstract-Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent findings on efficient attacks based on information leakage in caches have also brought the security issue up front. Design for security introduces even more restrictions and typically leads to significant performance degradation. This paper presents a novel cache architecture that can simultaneously achieve the above goals. Specifically, cache miss rates are reduced with dynamic remapping and longer cache indices, access-time overhead overcome with astute low-level circuit design, and information leakage thwarted by a security-aware cache replacement algorithm together with the performance enhancing mechanisms. We present both theoretical analysis and experimental results, using the SPEC2000 suite to evaluate the cache miss behavior, and CACTI and HSPICE to validate the circuit design. Our results show that the proposed cache architecture has low miss rates comparable to a highly associative cache and short access times and power efficiency close to that of a direct-mapped cache. At the same time it can thwart cache-based software side-channel attacks, providing both legacy and security-enhanced software a much higher degree of security. Additional benefits that the proposed cache architecture can bring, like fault tolerance and hot-spot mitigation, are also discussed briefly.

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“…A recent study observed up to approximately 20% power variation in an off-the-shelf set of nineteen 1 GB DDR3 DIMMs [19]. On-chip memory designers have tried to create process variation-aware memory subsystems [42,39,52,4] to address this issue, and multiple efforts have been made to minimize off-chip memory accesses via caching [59,31,50,21], OS-level [65,17,27], and DRAMlevel power management [14,40,27]. However, these designs required changes to existing memory configurations.…”

Section: Introductionmentioning

confidence: 99%

Variability-aware memory management for nanoscale computing

Dutt

Gupta

Nicolau

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-As the semiconductor industry continues to push the limits of sub-micron technology, the ITRS expects hardware (e.g., die-to-die, wafer-to-wafer, and chip-to-chip) variations to continue increasing over the next few decades. As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as minimize power consumption. The memory subsystem is one of the largest components in today's computing system, a main contributor to the overall power consumption of the system, and therefore one of the most vulnerable components to the effects of variations (e.g., power). This paper discusses the concept of variability-aware memory management for nanoscale computing systems. We show how to opportunistically exploit the hardware variations in onchip and off-chip memory at the system level through the deployment of variation-aware software stacks.

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Working with Process Variation Aware Caches

Cited by 19 publications

References 15 publications

Hardware/software approaches for reducing the process variation impact on instruction fetches

Hardware/software approaches for reducing the process variation impact on instruction fetches

A novel cache architecture with enhanced performance and security

Variability-aware memory management for nanoscale computing

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