Workload and power budget partitioning for single-chip heterogeneous processors

Wang, Hao; Sathish, Vijay; Singh, Ripudaman; Schulte, Michael; Kim, Nam Sung

doi:10.1145/2370816.2370873

Cited by 42 publications

(26 citation statements)

References 14 publications

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“…In order to model a heterogeneous address space, also taking into consideration the same simulators previously mentioned, the integration of the GPGPUsim into GemM5 CPU simulator is already implemented as indicated in [13]. Nevertheless, this combined infrastructure further increases simulation complexity, and therefore, significantly increases simulation times.…”

Section: Methodsmentioning

confidence: 99%

Insights on memory controller scaling in multi-core embedded systems

Marino¹,

2014

IJES

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Abstract:In recent years, the growth on the number of cores as well as the frequency of cores along different processor generations has proportionally increased bandwidth needs simultaneously in both CPU and GPU systems. In order to address the communication latency between CPU and GPU memories in recent implementation of heterogeneous mobile embedded systems with hard or firm real-time requirements, sharing the same address space adds significant levels of contention. In addition, when heterogeneous cores are simultaneously present in a single system, memory parallelism is significantly restricted by a small amount of memory controllers (MCs). As a strategy to approach these significant levels of memory pressure, it is proposed in this paper evaluations of the impact of scaling MCs up to 4-8 units -limited by motherboard size for embedded purposes. Our findings show that performance is enhanced by a factor of 4x when employing only CPU cores, 4.6x when only GPU cores and finally, 2x when both CPU and GPU cores are simultaneously considered.

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Section: Methodsmentioning

confidence: 99%

Insights on memory controller scaling in multi-core embedded systems

Marino¹,

2014

IJES

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“…For desktop platforms, there has also been efforts to exploit CPU and GPU cores present within a single chip [19,27,28]. In these platforms, coordination of CPU and GPU cores needs more consideration.…”

Section: State-of-the-artmentioning

confidence: 99%

Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs

Wächter

Merrett

Al-Hashimi

et al. 2017

Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia

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Heterogeneous Multi-Processor Systems-on-Chips (MPSoCs) containing CPU and GPU cores are typically required to execute applications concurrently. Existing approaches exploit applications executing in CPU and GPU cores at the same time taking into account performance and energy consumption for mapping and partitioning. This paper presents a proposal for mapping and partitioning of applications in CPU-GPU MPSoCs taking into account the temperature behavior of the system. We evaluate the temperature profiling to partition the applications between CPU and GPU. The profiling is done by measuring the temperature of the CPU and GPU cores while executing different applications at different partitions. Results shown up to 13% savings of average temperature of the chip while maintaining performance requirements. A lower thermal behavior represents a better long-term reliability (lifetime) of the SoC.

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“…In [23], Lee et al proposed thread-level-parallelism-aware cache management policies in CPU-GPU processors. Wang et al [36] proposed workload-partitioning mechanisms between the CPU and GPU to utilize the overall chip power budget to improve throughput. In [29], Paul et al characterized thermal coupling effects between CPU and GPU and proposed a solution to balance thermal and performance-coupling effects dynamically.…”

Section: Related Workmentioning

confidence: 99%

Coordinated energy management in heterogeneous processors

Paul

Ravi

Manne

et al. 2013

Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

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This paper examines energy management in a heterogeneous processor consisting of an integrated CPU-GPU for highperformance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types -a new and less understood problem.We examine the intra-node CPU-GPU frequency sensitivity of HPC applications on tightly coupled CPU-GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU-GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power-and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED^2) product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

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Workload and power budget partitioning for single-chip heterogeneous processors

Cited by 42 publications

References 14 publications

Insights on memory controller scaling in multi-core embedded systems

Insights on memory controller scaling in multi-core embedded systems

Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs

Coordinated energy management in heterogeneous processors

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