Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

Abstract

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

“…A pair of 175-JFET "÷2/÷4 Clock" demonstration IC chips from Wafer 10.1 were selected and separately prepared for the 60-day Venus environment test. As reported in [31] and [32], this technology demonstration IC provides a "base" frequency clock signal generator (a 21-stage ring oscillator) with electronically selectable divide by 2 or divide by 4 output signal frequencies achieved using two D-type flip flops and control signal logic. The complete functionality of this IC can be verified using only four input signals (SELECT input plus chip power lines +V DD , GND, and −V SS ) and one output signal.…”

“…The IC chips tested in this report were diced from a recent 4H-SiC JFET IC prototype wafer (designated "Wafer 10.1") fabricated at the NASA Glenn Research Center. The basic device structures, logic gate approach, fabrication process, circuit schematics, and more than 10,000 hours of 500 • C Earth-air oven-testing of chips from this wafer have been described in previous publications [31], [32]. The n-channel JFET (6 μm gate-length) and resistor IC topology with two levels of interconnect is effectively the same as employed for the "Wafer 9.2" ICs run in the previously reported 21-day Venus environmental test [33].…”

“…As of this writing, the only reports of months of stable T ≥ 460 • C semiconductor IC operation have been circuits based on integrated SiC JFETs and resistors tested in high-temperature ceramic packages in Earth-air atmosphere ovens [24]- [32]. In 2016, such SiC JFET IC chips successfully demonstrated 21 days (3 weeks) of operation in a high-fidelity reproduction the Venus surface environment comprised of the first 9 chemical atmospheric constituents (including sulfur dioxide and gaseous acids HCl and HF) at full Venus pressure (∼9.3 MPa, ∼92 Earth atmospheres) and ambient temperature (460 • C) [33].…”

“…A more-recent generation of prototype SiC JFET ICs developed and fabricated by NASA Glenn have now progressed to over a year of continuous operation at 500 • C in Earth air atmosphere ovens with complexity up-scaled to 195 transistors per IC [31], [32]. This upscaled level of integrated circuit complexity for ICs proven durable for months at T ≥ 460 • C is comparable to silicon chip complexities flown in 1970's era planetary exploration missions and Earth-orbiting satellites [15].…”

Stable Operation of AlGaN/GaN HEMTs for 25 h at 400°C in air

“…Wide-bandgap electronics have recently found use in aviation, space exploration, automotive and deep-well drilling applications. NASA Glenn Research center (GRC) has studied SiC JFETs (junction field effect transistors) for harsh environments for approximately a decade [3] and demonstrated reliable electronics operational at 500°C for a year [4]. High-temperature devices and Circuits in SiC have also been studied to a great extent in n-type metaloxide semiconductor (NMOS) and complementary metaloxide semiconductor (CMOS) [5]- [8], and BJT (bipolar junction transistor) architectures [9]- [18].…”