µW Pre-processing Unit for Virtual Sensors Based on Tri-axial Smart Accelerometers

Vita, Antonio De; Licciardo, Gian Domenico; Femia, Aldo; Benedetto, Luigi Di; Pau, Danilo

doi:10.1109/newcas44328.2019.8961264

Cited by 1 publication

(3 citation statements)

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“…The advantage of the CA structure with respect to other wellknown filter structures is summarized in Table IV, in which we show that the CA structure allows obtaining a saving of roughly 50% in terms of number of multipliers and registers under the same filter order. With a view to implement a custom low-power and low-resources HW solution, a fixedpoint (FI) coding has been used, because this allows to implement more compact arithmetic circuits with respect to their FP counterpart [24]. We determined the optimal wordlength, considering that the quantization of the filter coefficients causes a change in the frequency response with respect to the ideal one, with the possibility for the filter to become unstable.…”

Section: Pre-processing Operationsmentioning

confidence: 99%

“…Therefore, the acceleration vector needs to be represented in the Earthfixed reference frame, which is obtained by using the extracted gravity vector as reference. To this aim, the HWfriendly algorithm proposed in [24] has been used. In fact, the conventional methods for the reference frame transformation, such as Euler angles, quaternions, and Rodrigues' rotation formula, require the computation of complex mathematical functions (i.e.…”

Section: Pre-processing Operationsmentioning

confidence: 99%

“…The input of the pre-processing module is the 3-axis acceleration from the sensor. The pre-processing module corresponds to the circuitry proposed in [24], which is made up of 3 parallel FI-24 Booth multipliers, and 2 FI-24 cascaded adders. This allows to perform the transformation of the reference frame by means of an iterative processing, storing the intermediate results in 500 bytes register bank.…”

Section: A Pre-processing Modulementioning

confidence: 99%

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Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

Vita

Pau

Benedetto

et al. 2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. Aiming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.

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Section: Pre-processing Operationsmentioning

confidence: 99%

Section: Pre-processing Operationsmentioning

confidence: 99%

Section: A Pre-processing Modulementioning

confidence: 99%

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