The first generation of C-RAM memory is designed to greatly exceed (in density, write speed, endurance) the existing non-volatile memory solutions for space and to close the gap that exists between system requirements and availability. Based on the success of the 64 kb C-RAM program, we are designing a 4 Mb C-RAM product implemented in 0.25 µm radiation-hardened CMOS. In this paper we present a description of the architecture and design of the prototype 4 Mb chalcogenide non-volatile memory and provide schematic based simulation results showing memory operation.

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Static random access memory (SRAM) product for advanced space applications must demonstrate high performance to meet the ever increasing data rates of space systems and must be radiation hardened to ensure unfettered, reliable operation in the harsh environments of outer space. High performance and radiation hardness are not mutually exclusive. The challenge con*onting present day SRAM development is to concurrently achieve both of these objectives.An SRAM design evaluation methodology is described that uncovers limitations on performance, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Simulation model to hardware measurement correlation on two designs of radiation tolerant 4M S R A M product validates the evaluation methodology. The evaluation metbodology described herein can be universally applied to any SRAM design to ensure that the highest performance potential of the design is realized.