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The first generation of C-RAM memory is designed to greatly exceed (in density, write speed, endurance) the existing non-volatile memory solutions for space and to close the gap that exists between system requirements and availability. Based on the success of the 64 kb C-RAM program, we are designing a 4 Mb C-RAM product implemented in 0.25 µm radiation-hardened CMOS. In this paper we present a description of the architecture and design of the prototype 4 Mb chalcogenide non-volatile memory and provide schematic based simulation results showing memory operation.

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