No abstract

No abstract

A detailed analysis of hot-carrier-degraded NMOS and PROS devices with either n+ or p+ gates is presented. For this analysis, we utilized a new simulation tool which allows direct monitoring of the buildup of charge and interface states during the DC stress experiments. The impact of the work-function difference of the n+ and p+ gate material on the injection conditions of hot carriers into the gate oxide will also be considered. Our results indicate that both NMOS and PMOS FETs with p+ gates are superior regarding hot-carrier stability.

No abstract

No abstract