The reactive ion etching characteristics of gallium nitride (GaN) in silicon tetrachloride plasmas (SiCl4, 1:1/SiCl4:Ar, and 1:1/SiCl4:SiF4) in the pressure range between 20 and 80 mTorr have been investigated. For the pressure range investigated, etch rates are found to be essentially identical for the different gas mixtures and also invariant with pressure. However for all gas mixtures, etch rates increased monotonically with increasing plasma self-bias voltage exceeding 50 nm/min at 400 V. This is one of the highest etch rate ever reported for GaN. Smooth and anisotropic etch profiles are demonstrated for structures of submicrometer dimensions. The slight overcut observed in the etch profiles is attributed to the significant role of physical ion bombardment in the etching mechanism. Auger electron spectroscopy show that a wet etch in dilute HF is needed to clear the Si (in the form of SiOx) embedded in the near surface of GaN during etching thereby restoring etched surfaces to their virgin state.
The fabrication and performance of ultra-high-speed 0.3-m gate-length enhancement-mode high-electron-mobility transistors (E-HEMT's) are reported. By using a buried platinum-gate technology and incorporating an etch-stop layer in the heterostructure design, submicron E-HEMT devices exhibiting both high-threshold voltages and excellent thresholdvoltage uniformity have been achieved. The devices demonstrate a threshold voltage of + + +171 mV with a standard deviation of only 9 mV. In addition, a maximum DC extrinsic transconductance of 697 mS/mm is measured at room temperature. The output conductance is 22 mS/mm, which results in a maximum voltage gain (g g g m m m =g g g 0 ) of 32. The devices show excellent RF performance, with a unity current-gain cutoff frequency (f f f t t t ) of 116 GHz and a maximum frequency of oscillation (f f f max ) of 229 GHz. To the best of the authors' knowledge, these are the highest reported frequencies for lattice-matched E-HEMT's on InP.
The fabrication and characterization of an 11-stage ring oscillator utilizing integrated enhancement-and depletionmode (E/D-mode) high-electron mobility transistors (HEMT's) in the lattice-matched InAlAs/InGaAs/InGaAs material system is demonstrated. The 0.5-m gate length depletion-mode HEMT's (D-HEMT's) used in the circuit exhibit a threshold voltage (V V V T T T ) of 0365 mV with a standard deviation of 19 mV, while the enhancement-mode HEMT's (E-HEMT's) with identical gate length display a V V V T T T of 195 mV with a standard deviation of only 9 mV. The unity current gain cutoff frequency (f f f t t t ) for both devices is 70 GHz. The extremely high uniformity of the threshold voltages of these devices allowed for the implementation of a ring oscillator utilizing direct coupled FET logic (DCFL). At a supply voltage of 0.4 V, a room temperature propagation delay time ( pd ) of 22.4 ps/stage, and a corresponding power dissipation of 120 W/stage is measured, yielding a power delay product (PDP) of 2.65 fJ/stage. To the best of the authors' knowledge, this is the first demonstration of a circuit employing E/D-HEMT technology in the lattice-matched InP-based material system.
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