1997
DOI: 10.1109/55.585360
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0.3-μm gate-length enhancement mode InAlAs/InGaAs/InP high-electron mobility transistor

Abstract: The fabrication and performance of ultra-high-speed 0.3-m gate-length enhancement-mode high-electron-mobility transistors (E-HEMT's) are reported. By using a buried platinum-gate technology and incorporating an etch-stop layer in the heterostructure design, submicron E-HEMT devices exhibiting both high-threshold voltages and excellent thresholdvoltage uniformity have been achieved. The devices demonstrate a threshold voltage of + + +171 mV with a standard deviation of only 9 mV. In addition, a maximum DC extri… Show more

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Cited by 38 publications
(13 citation statements)
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“…C gs ≈ q · L g · dn S dV GS [3] where g ds is the output conductance, R S is the source resistance, and n S is the electron sheet density in the 2DEG channel. The R S is composed of contact resistances and resistances of the different parts of the epitaxial layer within the gate-source region.…”
Section: Resultsmentioning
confidence: 99%
“…C gs ≈ q · L g · dn S dV GS [3] where g ds is the output conductance, R S is the source resistance, and n S is the electron sheet density in the 2DEG channel. The R S is composed of contact resistances and resistances of the different parts of the epitaxial layer within the gate-source region.…”
Section: Resultsmentioning
confidence: 99%
“…This process, however, simultaneously produces a highly resistive uncapped region around the gate periphery due to side etching, which results in the fatal degradation of device performance. Pt-based buried-gate technology can be used to overcome this problem [225][226][227]. In general, InP HEMTs have an InGaAs channel layer (Indium content can be 53-75% depends upon application) and an InAlAs supply layer grown on the InP substrate using metal organic chemical vapor deposition (MOCVD) crystal growth technique.…”
Section: Developments In Indium Phosphide Hemtsmentioning
confidence: 99%
“…The gate metal, Pt/Ti/Pt/Au, was then deposited. After gate metal liftoff, the devices were annealed at 350 C for 60 s to produce a positive threshold voltage device [2]. After gate formation, the devices were passivated with PECVD SiN.…”
Section: Device Structure Growth and Fabricationmentioning
confidence: 99%