We describe a liner' for Cu-Damascene multilevcl ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects'. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (a-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and Nz sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (-30-60 M-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects. Introduction Many liners have been implemented in experimental Cu integration schemes. The family of Ta-based compounds has emerged prominently. Ta (P-phase) was first shown to be an excellent Cu diffusion barrier in 1986 by Hu et d 3 . It was since found4 that a low background level (e.g. < l o 7 Torr) of O2 or H 2 0 was responsible for decreasing Cu diffusivity through Ta grain boundaries. (Presumably, current studies that fmd reduced Ta barrier performance stem fiom the low base pressures of modem PVD systems, and could be helped by a controlled leak of 02.) Such a P-Ta(0) barrier was used in the first multilevel Cu integration in polyimide ILD', due to its optimal adhesion to the materials used6. For dualDamascene integration in Si022 however (see fig. 1 .), Ta and Ta2N7 lack adequate adhesion to SO2, whereas TaN/SiO2 adhesion is excellent ( fig. 2). On the other hand, Cu/TaN adhesion is relatively poor. In fact, the liner/ILD and Cdliner adhesion have conflicting dependencies on N% in TaN,. We believe it is essential to maximize adhesion at all interfaces, especially the Cu/liner one. This is both to resist delamination during processing or thermal stressing, and for electromigration resistance in fine Cu lines, where interfacial and surface migration play a large role*. As confirmed elsewhere', Cu E-M lifetimes are lower when against a TaN vs. a Ta liner. Unlike CdTaN, /W, and /TiN, the CdTa interface exhibits high wetting" and atomic-scale mixing". This occurs without alloying, which would consume Cu atoms. The Cu/Ta interface is thus uniquely optimal among the commonly studied candidates.Another essential liner quality which has not been addressed generally elsewhere and which is lacking in TaN or TiN, is the capacity for current-strapping (electromigration rcdundancy) by a suitably thin liner. In thc event of Cu defects or elcctromigration wearout, a propcr liner should prevent or dclay open-circuit failurc, cvcn at maximum rated currcnt concentrated in the liner. Such rcdundancy is achieved by the TiAh alloy ovedunder cladding in our AI(Cu) interconnects, and is a reliability requirement for our Cu interconnccts as well. DiscussiodData Our evaluation factors for designing a Cu Damascenc liner are shown in Table I, with results from screening of many candidat...

No abstract

Experiments have been undertaken to determine the length and width dependence of electromigration-induced failure time in aluminum thin-film conductors. A statistical model is presented and compared to the experimental data. The significance of the experimental data and the statistical model are discussed in terms of randomly distributed structural defects which produce flux divergences during electromigration.

Electrochemical fabrication of PbSn C4s (controlled collapse chip connection) offers significant cost, reliability, and environmental advantages over the currently employed evaporation technology. A continuous seed layer is required for through-mask electrodeposition of the solder alloy. This layer becomes the ball limiting metallurgy (BLM) for the solder pad after etching. The seed layer metallurgy and the BLM etching are crucial to obtaining mechanically robust C4s. In the present study, the issues related to the selection of seed layer metallurgy, uniformity of plating and etching, and mechanical integrity of C4s have been investigated. The resul~s demonstrate the feasibility of electrochemically fabricating highly reliable PbSn (97/3) C4 structures with a high degree of dimensional uniformity on a variety of wafer sizes ranging up to 200 ram.

No abstract