No abstract

MITLL has developed a three dimensional integrated circuit (3DIC) technology that exploits the advantages of SOI technology to enable wafer stacking and micrometer-scale vertical interconnection of fully fabricated circuit wafers [1,2]. This paper presents the first radiation test results on this 3DIC technology. 3D fabrication process Devices and circuits are fabricated by transferring and interconnecting fully fabricated 150-mm SOI substrates to a base wafer, also a fully fabricated 150-mm SOI substrate. Wafer-level integration is enabled by bonding oxide films at low temperature. High circuit density is enabled by fabricating 3D-vias to interconnect the different tiers. Figure 1 shows a cross-section scanning electron micrograph of a 3DIC wafer showing three FDSOI CMOS tiers, eleven metal layers, and 3D vias interconnecting tiers 1, 2 and 3. On tiers 2 and 3, FETs are inverted so that front gates are below the SOI , the BOX is above the SOI, and the original silicon substrate was removed and replaced by deposited oxides.

RF amplifiers are demonstrated using a threedimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.

Advances in high‐frequency resonant‐tunneling‐diode (RTD) oscillators are described. Oscillations up to a frequency of 420 GHz have been achieved in the GaAs/AlAs system. Recent results obtained with In0.53 Ga0.47As/AlAs and InAs/AlSb RTDs show a greatly increased power density and indicate the potential for fundamental oscillations up to about 1 THz. These results are consistent with a lumped‐element equivalent circuit model of the RTD. The model shows that the maximum oscillation frequency of the GaAs/AlAs RTDs is limited primarily by series resistance, and that the power density is limited by low peak‐to‐valley current ratio.