Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers

Chen, C. L.; Chen, C. K.; Yost, D.; Knecht, J.M.; Wyatt, P.W.; Burns, James R.; Warner, K.; Gouker, P.; Healey, P.; Wheeler, Bruce; Keast, C.L.

doi:10.1109/smic.2009.4770536

Cited by 11 publications

(5 citation statements)

References 2 publications

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“…With both direct integration and advanced 3D integration techniques, the wire (and/or pad capacitance) can be quite low. Using, for example, direct integration, the total via/wire capacitance has been estimated to be 5fF [24] and using wafer bonding based 3D integrated through-oxide-vias (TOV) [32], the via capacitance has been measured to be ~2fF. Therefore with TOVs, the ground and signal vias will add a total of 4fF of capacitance, similar to the direct integration case.…”

Section: Implementation Of This Technique Adds An Energy Per Bit Over...mentioning

confidence: 99%

An ultralow power athermal silicon modulator

et al. 2014

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Silicon photonics has emerged as the leading candidate for implementing ultralow power wavelength–division–multiplexed communication networks in high-performance computers, yet current components (lasers, modulators, filters and detectors) consume too much power for the high-speed femtojoule-class links that ultimately will be required. Here we demonstrate and characterize the first modulator to achieve simultaneous high-speed (25 Gb s−1), low-voltage (0.5 VPP) and efficient 0.9 fJ per bit error-free operation. This low-energy high-speed operation is enabled by a record electro-optic response, obtained in a vertical p–n junction device that at 250 pm V−1 (30 GHz V−1) is up to 10 times larger than prior demonstrations. In addition, this record electro-optic response is used to compensate for thermal drift over a 7.5 °C temperature range with little additional energy consumption (0.24 fJ per bit for a total energy consumption below 1.03 J per bit). The combined results of highly efficient modulation and electro-optic thermal compensation represent a new paradigm in modulator development and a major step towards single-digit femtojoule-class communications.

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Section: Implementation Of This Technique Adds An Energy Per Bit Over...mentioning

confidence: 99%

An ultralow power athermal silicon modulator

et al. 2014

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“…The technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronics popularly referred to as extending Moore's Law [2]. SOI process has been developed intended for radio frequency (RF) applications [3]. The inclusion of enhanced sapphire substrate allows the complementary metal-oxide semiconductor (CMOS) node to have a high isolation, high linearity, and electrostatic discharge (ESD) tolerance.…”

Section: Silicon-on-insulator Wafermentioning

confidence: 99%

A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

Bacquian¹,

Gomez²

2020

JERR

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The relentless advancement and trends on thinner packages have become the focus in the semiconductor manufacturing industry. The requirement of thinner packages also demands a thinner vertical structure of the semiconductor electronic design. As a major contributor on the vertical structure of the electronic package, die or wafer is also essential to go thinner. As the wafer becomes thinner, various problems may occur during transport and even the backgrinding process itself. Wafer warpage is one of the main concerns during the wafer backgrinding process. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poor grinding and broken wafer. Wafer backgrinding stress and backgrinding tape tension also contribute to the effect on wafer warpage. Challenges exist in processing different silicon wafer technology, particularly the silicon-on-insulator (SOI) technology. Evaluating the effect of backgrinding tape selection and vacuum efficiency to eliminate such warpage is presented in this paper.

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“…The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronics colloquially referred to as extending Moore's law [2][3]. SOI process has been developed so as to be used for RF applications [4]. The inclusion of enhanced sapphire substrate allows the complementary metal-oxide semiconductor (CMOS) node to have a high isolation, high linearity, and electrostatic discharge (ESD) tolerance.…”

Section: Silicon On Insulator Wafermentioning

confidence: 99%

A Study of Vacuum Efficiency for Silicon on Insulator Wafers

Bacquian¹,

Gomez²

2019

JERR

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The development on thinner packages has become the trend and focus in semiconductor packaging industry. The necessity of thinner packages also entails a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the back grinding process, itself. Wafer warpage is one of the main concerns during the process. The effect of proper vacuuming will play major role in processing SOI wafers. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poorer grinding and worst broken wafer. Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior back grinding. Evaluating the effect of vacuum efficiency to eliminate such warpage is discussed on this technical paper.

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Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers

Cited by 11 publications

References 2 publications

An ultralow power athermal silicon modulator

An ultralow power athermal silicon modulator

A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

A Study of Vacuum Efficiency for Silicon on Insulator Wafers

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