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As integrated circuits for high performance CMOS devices scale down to < = 10 nm dimension, further reductions in capacitance are vitally important for device performance. It is important to reduce capacitance in the FEOL and BEOL device structures while maintaining fabrication integration robustness. This paper presents an overview of material and process technology requirements for FEOL air spacer and BEOL air gap formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume. The void dimension and volume in airgap/air spacer structures can be controlled with various dielectric deposition processes and materials to facilitate subsequent process fabrication steps, and ultimately to build a robust device with substantial capacitance reduction.