On the basis of an individual treatment center's management risks, annual aneurysmal rupture rates can be estimated that justify treatment in this difficult patient population. Despite recent controversy regarding aneurysmal hemorrhage rates, we think that symptomatic unruptured aneurysms should be treated and good results can be achieved, even in older patients.

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− This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and P out decrease with increasing device width because of a decrease in the maximum oscillation frequency (f max ) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches f max . The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.

An ultralow-standby-power technology has been developed in both 0.18-m and 0.13-m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m 2 and 2.34 m 2 , corresponding respectively to the 0.18-m and 0.13-m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25ЊC and is less than 400 fA per cell at 1.5 V, 85ЊC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.