No abstract

No abstract

The ever increasing demand for denser Flash memories leads to the multilevel (ML) storage approach, where any memory cell is programmed to one of m = 2 n predetermined states and can hence store n bits [1,2]. This 64Mb 4-level cell (2b/cell) Flash memory device uses a triple-metal triple-well p-bulk 0.18µm CMOS process featuring shallow trench isolation (STI) for denser memory array packing. The device (programming channel hot electron injection, erasing Fowler-Nordheim tunneling) is organized in 64 identical sectors (512 rows by 1024 columns) with a NOR architecture. Data input/ output (I/O) can be selected (16 or 32). A dedicated pad supplies the I/O buffers to allow direct interfacing to external low voltage (i.e., 1.8V) devices, as is required in most portable applications. The pullup p-channel transistor in the output buffer is driven with a negative-bootstrapped voltage to provide adequate drive capability at low supply voltage (switching time is 10ns with a 50pF load at 1.8V). All high voltages needed for memory operation (programming, erasing, and reading) are generated on-chip by charge-pump voltage multipliers, starting from the single 3V supply. Reading can be both in asynchronous mode (130ns access time) and in burst mode. For the latter, continuous and pipeline modes are provided, with up to 50MHz data rate and different data output latency and burst size. Both sequential and interleaved data output is available. To achieve sufficiently tight threshold voltage distributions, staircase-gate voltage programming and program and verify techniques are used [2]. Program throughput is increased by parallel programming: 16 words (256 bits) are loaded into a buffer, and the entire writing procedure is then performed under the control of an internal routine. The latter also takes into account the limited current source capability of the charge-pump program-voltage generator. Program throughput is 6µs/B (192µs for an entire buffer). Erasing is by applying negative voltage to the gate and a staircase positive voltage to both source and substrate to improve reliability. All algorithms are generated on-chip. These include writing routines, erase suspend and erase resume facilities, sector protection (in any user-chosen configuration), and common Flash memory interface (CFI). Up to 100,000 erase/program cycles are guaranteed for any sector. To ensure reliability, error correction code (ECC) techniques are integrated. A 2-level hierarchical approach for both row and column decoding ensures performance and reliability and saves chip area. The eight sectors placed in the same horizontal group share the global row decoder and, hence, the global wordlines (128). Any global word-line controls 4 local word-lines in each of the 8 respective sectors (one local row decoder per sector is provided) (Figure 16.6.1). A similar approach is adopted for column decoding. A global decoder structure, supplied by a charge pump, provides address switching with minimum short-circuit current. The local column decoder is made up of one n-c...

No abstract

No abstract