Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as intermediate carrier and wiring device for IC components like logics, memories and sensors. Due to custom specific front and back side wiring interposers enable to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. High density copper filled TSVs with high aspect ratio as well as high density multi layer wiring using electro plated copper as conductive material and low loss dielectrics enable high performance signal transmission at interposer level without serious losses by parasitic effects. This paper presents the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer level assembly with IC components. Special focus is drawn on the TSV formation process including via etching, isolation and filling as well as front side high density wiring and subsequent backside processing of the thin TSV wafers. In this context, also temporary wafer to wafer bonding which is required for backside processing of thin TSV wafers is discussed. The final interposers which carry one or more IC components have lateral dimensions up to several square centimeters and thicknesses between 50-100 m. They include up to several thousands of TSVs per device with a single electrical resistance between 4.9-5.7 mOhms. All processes were run using production equipment at 200 mm wafers

In this paper we describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing. Thin wafer handling is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures. The work was done as evaluation study to prove the compatibility of a thin wafer handling system with standard processes used for thinning and backside processing of "via-first" TSV wafers as well as for thinning of bumped wafers. The used thin wafer handling system is based on perforated carrier wafers, which are bonded by an adhesive to the customer wafer and de-bonded by solvent release of the adhesive. All wafers used in this work had 200 mm format. The evaluation was run systematically in three major phases. In the first phase the main process scenarios, which require thin wafer handling, were defined. In a second phase setup trials for bonding, thinning, backside processing and debonding we re run on monitor wafers with different types of front side topography, but without TSVs. After finishing the setup trials in a third phase, the monitor wafers were replaced by wafers with copper filled TSVs, which were fabricated in "via-first" technology. Using the established thin wafer handling and processing sequence, silicon interposer wafers with 55 m thickness were manufactured. The measured via chains have via pitches of 28 m using 15 m via diameter

A common requirement for all current and future TSV (Through Silicon Via) applications is the ability to handle and process thinned Silicon Wafers, usually in the range of 150m or much below. Silicon Wafers of this thickness cannot be handled without support as wafers with the standard thickness. One solution to tackle this problem is the use of wafer-support-systems (WSS), in which the thinned wafers are bonded temporarily to a carrier wafer, which gives the wafer mechanical stability. Another solution for handling are carrierless systems, in which the wafer is modified in a way that it is thin and mechanically rigid at the same time. Existing carrierless systems provide mechanical integrity for the wafer, but lack the full integration into backside processing. In this paper, we present a carrierless approach that provides mechanical stability and can be integrated into backside processing technology at the same time. We present results of a carrierless wafer with a th ickness of 60m only which has undergone a bumping process at the backside

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