No abstract

No abstract

The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (V t1 ), holding voltage (V h ) and secondary breakdown current (I t2 ). Eventually, it can be found that how to sketch the layout pattern of an nLDMOS is a very important issue in the anti-ESD consideration. The waffle-type nLDMOS DUT is poor contribution to I t2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the I t2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared with a traditional striped-type (reference) nLDMOS device. The ESD abilities of traditional striped-type and waffle-type nLDMOS devices with an embedded SCR (pnp-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR (pnp-manner arrangement) is a good structure for the anti-ESD reliability in high-voltage applications.

No abstract

This paper aimed at the study of layout dependence on ESD/LU reliabilities in the O.35um 3.3V low-voltage triggered silicon-controlled-rectifier (LVTSCR) DUTs. In this work, the parameter of channel L in an nMOS, the parameter S of an SCR are varied to study the influence on trigger voltage (Vtt), holding voltage (Vh) and secondary breakdown current (112), Eventually, it can be concluded that the layout illustration of type-2 has a higher 112 than that of type-I, i.e., the ratio of (ldtype-2/(ldtype-1 > 1.3 among all the LVTnSCRs. Meanwhile, the holding voltages of SCR devices are latch-up (LU) free while operated at 3.3V.Therefore, the type-2 layouts of SCR device are so excellent structure in the ESD/LU reliability considerations for power management applications.