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The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64m CPU's, a shared 512KB L2 cache, a DDR memory controller, and integrated UO. All major blocks of the processor are connected together via the ZBbusTM; a high speed split transaction fully coherent multi processor bus.Three Gigabit Ethernet MAC's enable a direct interface to network elements. High-speed system U 0 is provided using AMD's Lightning Data Transport (LDTm) U 0 fabric and a 66MHz PCI bus. The die measures 14.2" by 13.3" in a bulk 0.15pm CMOS technology and has a power dissipation of 13W at 1.2V and 1GHz.

A unique LVS (layout-versus-schematic) methodology has been developed for the verification of a four-core microprocessor with multiple power domains using a triple-well 90-nm CMOS technology. The chip is migrated from its previous generation that is for a twin-well process. Due to the design reuse, VDD and GND are designed as global nets but they are not globally connected across the entire chip. The standard LVS flow is unable to handle the additional design complexity and there seems to be no published literature tackling the problem. This paper presents a two-phase LVS methodology: a standard LVS phase where power and ground nets are defined as global nets and a multi-power-domain LVS phase where power and ground nets are treated as local nets. The first phase involves verifying LVS at the block level as well as the full-chip level. The second phase aims at verifying the integrity of the multi-power-domain power grid that is not covered in the first phase LVS. The proposed LVS methodology was successfully verified by real silicon.

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