In this work, flexible InGaZnO (IGZO) synaptic thin-film transistors (TFTs) with different gate dielectric layers are fabricated and analyzed to investigate the effect of the gate insulator of flexible IGZO synaptic TFTs in terms of weight window and retention characteristics. The gradual weight modulation of these devices comes from the migration of hydrogens in the Al 2 O 3 layer deposited by low-temperature atomic layer deposition and can be controlled by gate bias. In addition, the learning behaviors with identical and incremental pulse schemes are verified for a linear weight modulation, and its effect in pattern recognition accuracy is studied considering device variation and retention properties in a 784 × 10 fully connected neural network with handwritten digit images.

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Hardware-oriented neuromorphic computing is gaining great deal of interest for highly parallel data processing and superb energy efficiency, as the candidate for replacement of conventional von Neumann computing. In this work, a novel synaptic transistor constructing the neuromorphic system is proposed, fabricated, and characterized. Amorphous indium-gallium-zinc-oxide (α-IGZO) and Al 2 O 3 are introduced as the channel and gate dielectric materials, respectively. Along with the high functionality and low-temperature processing viability, geometric peculiarity featuring extended gate structure improves the performances of the proposed transistor as synaptic component in the neuromorphic system. The insight into the substantial effect of optimal device structure design on energy efficiency is highlighted.IINDEX TERMS Hardware-oriented neuromorphic computing, parallel data processing, energy efficiency, synaptic transistor, amorphous indium-gallium-zinc-oxide, extended gate, device structure design Jong-Ho Bae received the B.S. degree in electrical engineering

Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap ( ph ) photonic energy ( ph = 0 943 eV, opt = +5 dBm), which is less than the silicon bandgap ( = 1 12 eV), is employed for the optical subthreshold current characterization of interface states in the photoresponsive energy band. We applied the OSCM method under a subbandgap photonic excitation to MOS systems with a poly-Si gate and verified a U-shaped distribution of interface trap density it = 10 10 10 12 eV 1 cm 2 for n-and p-type MOSFETs with = 30 m 1 2 m.