We have studied the chemical vapor deposition of copper from 1,5-cyclooctadiene Cu(I) hexafluoroacetylacetonate, a moderately volatile yellow cystalline solid. It yields pure copper by pyrolytic decomposition at 150–250 °C, produces copper films with near bulk resistivity, and has the advantage of being air stable at room temperature.

We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.

Arrays of nozzles of uniform size false(≃25×25 μm2false) and spacing (≃0.3 mm) suitable for high quality and high speed ink‐jet printing have been fabricated by the anisotropic etching of holes through (100) Si wafers using conventional Si‐processing techniques. The etchant used is a mixture of pyrocatechol, ethylene diamine, and water. The nozzles are well‐defined truncated, square pyramidal cavities bounded by 4 convergent {111} planes. The square orifice, side WO , is given by WO=WB−2 tnormalSi , where WB is the side of the square base and tnormalSi the wafer thickness. Successful fabrication of these silicon microstructures requires the application of well‐controlled patterning and etching processes and the selection of a uniform, defect‐free, accurately oriented single crystal substrate.

Planarization of VLSI interconnect structures is recognized as a crucial element in advanced BEOL. In this paper a structure is presented which uses full oxide planarization before the first and second metal layers, W studs for contacts and interlevel vias, and Ti,iA1(2S%Cu)/Si metal lines patterned by RIE. This structure has been successfully implemented on both BEOL test sites and in device runs to fabricate a selectively scaled 0Spm channel length 64Kb high-performance CMOS SRAM chip. Electrical testing results show contact resistances and metal test site yields equal or better than that achieved with metal lift-off processing. Functional testing of the 64Kb S R A M produced many chips with better than 90% yield, also equal or better than that achieved with a non-planarized lift-off process. Use of the M2 level in this chip design as a bit line strap reduced access time from 11 ns without M2 to roughly 6 ns with M2.N o degradation of device characteristics due to the BEOL processing could be detected.

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