This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.

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High quality GaAs is selectively grown in 40 nm width Shallow Trench Isolation patterned structures. The patterned wafers have a V-shape Si (111) surface obtained by Tetramethylammonium hydroxide etching. By employing a SiCoNi™ pre-epi clean and two-step growth procedure (low temperature buffer and high temperature main layer), defects are effectively confined at the trench bottom, leaving a dislocation-free GaAs layer at the upper part. The high crystal quality is confirmed by transmission electron microscopy. Scanning spreading resistance microscopy indicates a high resistance of GaAs. The process conditions and GaAs material quality are highly compatible with Si technology platform.

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