Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

The development of SiC bulk and epitaxial materials is reviewed with an emphasis on epitaxial growth using high-throughput, multi-wafer, vapor phase epitaxial (VPE) warm-wall planetary reactors. It will be shown how the recent emergence of low-cost high-quality 100-mm diameter epitaxial SiC wafers is enabling the economical production of advanced wide-bandgap Power–Switching devices.

A new chemical mechanical polishing process (ACMP) has been developed by the Penn State University Electro-Optics Center for producing damage free surfaces on silicon carbide substrates. This process is applicable to the silicon face of semi-insulating, conductive, 4H, 6H, onaxis and off-axis substrates. The process has been optimized to eliminate polishing induced selectivity and to obtain material removal rates in excess of 150nm/hour. The wafer surfaces and resultant subsurface damage generated by the process were evaluated by white light interferometery, Transmission Electron Microscopy (TEM), Atomic Force Microscopy (AFM), and epitaxial layer growth. Residual surface damage induced by the polishing process that propagates into the epitaxial layer has been significantly reduced. Total dislocation densities measured on the ACMP processed wafers are on the order of the densities reported for the best as grown silicon carbide crystals [1]. Characterization of high electron mobility transistors (HEMTs) grown on these substrates indicates that the electrical performance of the substrates met or exceeded current requirements [2].

Low dislocation density and even micropipe free substrates open up a great opportunity to produce high quality epitaxial layers. The epi-layer will become more sensitive to the epitaxial process itself and less dependent on varying substrate quality. Results presented here indicate a strong dependence of the epitaxial layers' growth mode and surface roughness on the substrates' dislocations and domain structure. Thick epitaxial layers grown on near on-axis wafers, both C-face and Si-face, show very similar growth behaviors as for physical vapor transport (PVT) grown crystals. The mix between step-flow and dislocation driven growth on near on-axis C-face chemical vapor deposition (CVD) grown epi-layers (30 μm thick) is resulting in a as smooth, and measured surface roughness is as low, as for growth on 8o off-axis substrates.Surface roughness, Ra, measured on a 50 μm thick epitaxial layer, grown on a low EPD (1E+4 cm-2) 8o off-axis micropipe free substrate, was as low as 1.0 nm (2.98x2.32 mm area).