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This work shows the benefits of using Plasma Nitrided gate oxide which supports the gate leakage requirements for 6Snm plarform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with loff @3nA/um, Vdd=0.9V for 65nm GP requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gafe leakage offers benefits in ternis of a 4.r reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability

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